NXP Semiconductors
UM11636
KITPF5200SKTEVM evaluation board
Click the
Start
button to start communication with the PF5200.
At this point, the State indicator displays
CONNECTED
and PF5200 header text changes
from red to green.
Usually, when connected, the next step is to load a script that is written to the Mirror
register. This must be done in Test mode.
5.2.3.2.2 I
2
C CRC enablement
The PF5200 I
2
C communication bus can be configured to manage an extra CRC byte.
This option is selected during OTP by setting the OTP_I2C_CRC_EN bit. The FRDM-
KL25Z must be notified when the OTP_I2C_CRC_EN is enabled in order to correctly
manage the I
2
C communication. That notification is provided by
I2C CRC
checkbox.
If OTP_I2C_CRC_EN is not enabled in the PF5200, no action is required by the user and
the
I2C CRC
box can be left unchecked.
If OTP_I2C_CRC_EN is enabled, the user must select
TBB-MODE
in the Mode box and
check the
I2C CRC
box. The GUI then checks if the PF5200 OTP_I2C_CRC_EN bit is
enabled. If the GUI verifies that the OTP_I2C_CRC_EN bit is enabled, the selection is
valid and the FRDM-KL25Z is able to manage the I
2
C CRC.
If the check indicates that the OTP_I2C_CRC_EN bit is not enabled, the PF5200
is not able to manage the I
2
C CRC and the following error message is displayed:
“
WARNING:I2C_CRC is not enabled in PF52
”.
5.2.3.2.3 Secure Write Mode enablement
PF5200 provides a Secure Write mechanism for specific bits that are critical to the
functional safety of the device.
Secure Write sequence request actions from both PMIC and MCU. PMIC actions are
enabled by
OTP_I2C_SECURE_EN
, and MCU action are enabled by
Secure Write
checkbox. This mechanism is fully operatives when both PMIC and MCU actions are
enabled.
UM11636
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
User manual
Rev. 2 — 13 December 2021
24 / 51