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NXP Semiconductors
UM11723
KITPF5200FRDMEVM evaluation board
the following figure, some fields are unavailable when OTP_PWRDN_MODE is set to
sequential instead group.
The Sequence diagram graph displays the power-up/power-down sequence.
The x-axis of the Sequence diagram can be set to either time mode (displays the
sequence in increments of time) or slot mode (displays the sequence in terms of
the assigned sequence slots). To change this setting, go to
View / OTP sequence
diagram mode
and select the mode.
– SW Regulators tab:
sets OTP Parameters for switcher 1 (SW1) and switcher 2
(SW2). The SW miscellaneous window on the right allows SW1 and SW2 to be
configured as single phase or dual phase. The block diagram window displays a
block diagram for the current device. Note that, because the PF5200 runs in PWM
UM11723
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© NXP B.V. 2021. All rights reserved.
User manual
Rev. 1 — 8 December 2021
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