NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

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MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
4-18 Freescale Semiconductor
4.11 Modem SPI Recursive Transactions
The MC1321x SPI also incorporates a recursive or ‘data burst’ transaction capability. This allows multiple
sequential SPI registers to be accessed with only one header field. Recursive reads and writes provide
significant reduction in SPI overhead and a corresponding increase in programming speed.
1. The primary intent is for the software to be able to rapidly configure the modem.
2. Recursive reads and writes are convenient for accessing SPI register values which extend beyond the
16-bit SPI register format. Examples include writing Timer Comparator values (tmr_cmp1[23:0]
through tmr_cmp4[23:0]) and reading the Time Stamp (timestamp[23:0]).
3. Recursive access capability enables the contents of modem Packet RAM to be read or written in
an expedient manner.
4.11.1 Recursive SPI Register Read
Recursive register reads are invoked in an identical manner to singular read operations, however, by
holding CE asserted for additional SPI bursts after the first 16-bit data payload is shifted out, the contents
of the next SPI register address is made available on the MISO pin. An internal SPI register address pointer
is automatically incremented during recursive reads to point to the next sequential SPI register location.
For each subsequent set of 2 SPI bursts, SPICLK shifts out the contents of the next register address.
This sequence repeats as long as the CE is held asserted, allowing multiple sequential register contents of
the SPI to be read starting at the header address. As the recursive read progresses, the SPI register address
pointer continues to increment. When the address pointer reaches 63 decimal (the maximum implemented
SPI register), the address pointer ‘rolls over’ to Address 03 and begins incrementing again. Address 03 is
chosen to avoid the Program Reset function at Address 00 and the Rx Packet RAM and Tx Packet RAM
at Addresses 01 and 02, respectively.
4.11.2 Recursive SPI Register Write
Recursive writes are invoked in an identical manner to singular write operations. But, by holding CE
asserted for additional SPI bursts after the first 16-bit data payload is shifted in, the contents of the next SPI
register address can be programmed. An internal SPI register address pointer is automatically incremented
during recursive writes to point to the next higher sequential SPI register location. For each subsequent set
of 2 SPI bursts, SPICLK shifts in the write data to the next register address.
This sequence repeats as long as the CE is held asserted, allowing multiple sequential register contents to
be written starting at the header address. As the recursive write progresses, the SPI register address pointer
continues to increment. When the address pointer reaches 63 decimal (the maximum implemented SPI
register), the address pointer ‘rolls over’ to Address 03 and begins incrementing again. Address 3 is chosen
to avoid the Program Reset function at Address 00 and the Rx Packet RAM and Tx Packet RAM at
Addresses 01 and 02, respectively.