NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

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Analog to Digital (ATD) Module
MC1321x Reference Manual, Rev. 1.6
20-4 Freescale Semiconductor
20.3.1 Mode Control
The ATD has a mode control unit to communicate with the sample and hold (S/H) machine and the SAR
machine when necessary to collect samples and perform conversions. The mode control unit signals the
S/H machine to begin collecting a sample and for the SAR machine to begin receiving a sample. At the
end of the sample period, the S/H machine signals the SAR machine to begin the analog-to-digital
conversion process. The conversion process is terminated when the SAR machine signals the end of
conversion to the mode control unit. For V
REFL
and V
REFH
, the SAR machine uses the reference potentials
to set the sampled signal level within itself without relying on the S/H machine to deliver them.
The mode control unit organizes the conversion, specifies the input sample channel, and moves the digital
output data from the SAR register to the result register. The result register consists of a dual-port register.
The SAR register writes data into the register through one port while the module data bus reads data out
of the register through the other port.
20.3.2 Sample and Hold
The S/H machine accepts analog signals and stores them as capacitor charge on a storage node located in
the SAR machine. Only one sample can be held at a time so the S/H machine and the SAR machine can
not run concurrently even though they are independent machines. No DC level correction,
channel-to-channel gain adjust, or other data acquisition functions are currently performed on the input
analog signals
. Figure 20-2 shows the placement of the various resistors and capacitors.
Figure 20-2. Resistor and Capacitor Placement
When the S/H machine is not sampling, it disables its own internal clocks. The input analog signals are
unipolar. The signals must fall within the potential range of V
SSAD
to V
DDAD
. The S/H machine is not
required to perform special conversions (i.e., convert V
REFL
and V
REFH
).
Proper sampling is dependent on the following factors:
• Analog source impedance (the real portion, R
AS
)
This is the resistive (or real, in the case of high frequencies) portion of the network driving the
analog input voltage V
AIN
.
+
R
AIN1
R
AS
C
AS
C
AIN
R
AIN2
R
AIN3
R
AINn
ATD SAR
ENGINE
CHANNEL
SELECT 0
CHANNEL
SELECT 1
CHANNEL
SELECT 2
CHANNEL
SELECT n
.
.
.
INPUT PIN
INPUT PIN
INPUT PIN
INPUT PIN
–
V
AIN