MCU Parallel Input/Output
MC1321x Reference Manual, Rev. 1.6
13-8
Freescale Semiconductor
13.5
Stop Modes
Depending on the Stop Mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
•
When the MCU enters Stop1 Mode, all internal registers including general-purpose I/O control and
data registers are powered down. All of the general-purpose I/O pins assume their reset state:
output buffers and pullups turned off. Upon exit from Stop1, all I/O must be initialized as if the
MCU had been reset.
•
When the MCU enters Stop2 Mode, the internal registers are powered down as in Stop1 but the I/O
pin states are latched and held. For example, a port pin that is an output driving low continues to
function as an output driving low even though its associated data direction and output data registers
are powered down internally. Upon exit from Stop2, the pins continue to hold their states until a 1
is written to the PPDACK bit. To avoid discontinuity in the pin state following exit from Stop2, the
user must restore the port control and data registers to the values they held before entering Stop2.
These values can be stored in RAM before entering Stop2 because the RAM is maintained during
Stop2.
•
In Stop3 Mode, all I/O is maintained because internal logic circuitry stays powered up. Upon
recovery, normal I/O function is available to the user.
NOTE
For low power modes, unused GPIO including unpinned-out signals must
be initialized.
13.6
Parallel I/O Registers and Control Bits
This section provides information about all registers and control bits associated with the parallel I/O ports.
Refer to tables in
for the absolute address assignments for all parallel I/O
registers. This section refers to registers and control bits only by their names. A Freescale-provided equate
or header file normally is used to translate these names into the appropriate absolute addresses.
13.6.1
Port A Registers (PTAD, PTAPE, PTASE, and PTADD)
Port A includes eight pins shared between general-purpose I/O and the KBI module. Port A pins used as
general-purpose I/O pins are controlled by the port A data (PTAD), data direction (PTADD), pullup enable
(PTAPE), and slew rate control (PTASE) registers.
If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as
an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of
PTAD will return the logic value of the corresponding pin, provided PTADD is 0.
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