NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

Страница: 81 / 372

MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
Freescale Semiconductor 4-5
4.5.2 Modem SPI Byte Burst Operation
The SPI port of the MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. Although
a MC1321x transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in
Figure 4-3 .
Figure 4-3. Modem SPI Burst Timing Diagram
Because the MCU is embedded in the SiP and the modem only supports one clock format, the MCU SPI
must be programmed for this clock mode, i.e., clock phase control bit CPHA = 0 and the clock polarity
control bit CPOL = 0. In addition, the MSB-first option must be selected.
Table 4-2. Modem SPI Timing Specifications
Symbol Parameter Min Typ Max Unit
T0 SPICLK period 125 ns
T1 Pulse width, SPICLK low 50 ns
T2 Pulse width, SPICLK high 50 ns
T3 Delay time, MISO data valid from falling SPICLK 15 ns
T4 Setup time, CE low to rising SPICLK 15 ns
T5 Delay time, MISO valid from CE low 15 ns
T6 Setup time, MOSI valid to rising SPICLK 15 ns
T7 Hold time, MOSI valid from rising SPICLK 15 ns
1 2 3 4 5 6 7 8
CE
SPICLK
T1
T2 T4
T0
SPI Burst
Valid
T5
T6
T3
Valid
T7
MISO
MOSI
Valid