NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

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MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
4-16 Freescale Semiconductor
Figure 4-12. SPI Singular Read Access
Figure 4-13 shows a write access transaction.
Figure 4-13. SPI Singular Write Access
4.9.2 SPI Singular Transaction Protocol
A SPI transaction is divided into a header field and a payload. The header field is always 8 bits, while the
payload data is in multiples of 2 bytes or 16 bits. A singular SPI transaction contains 24 bits of information.
The header field contains a R/W bit and a 6-bit register address, as shown in
Figure 4-14 .
Figure 4-14. SPI Header and Payload Definition
The R/W bit identifies the transfer as a read (R/W =1) or write (R/W =0). The lower 6 bits in the header
determines which of the 64 possible SPI locations is to be accessed for a read or write operation although
not all possible addresses are implemented. The register address field also provides the starting address for
a recursive read or write operation as described later. The register data is presented MSB first.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CE
SPICLK
MOSI
1 2 3 4 5 6 7 8
MISO
Valid data
Valid data Valid data
Header Payload
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CE
SPICLK
MOSI
1 2 3 4 5 6 7 8
MISO
Valid data Valid data Valid data
Header Payload
0