NEC PlasmaSync PX-42VM1G, Руководство по обслуживанию

Страница: 109 / 172

6-4
CIRCUIT DESCRIPTION
(12) Panel link block
In the case of RGB3 input, the digital RGB signal input fed from the PL1 connector comes in the serial
data, which are then converted into the parallel data at the Panel Link receiver of IC7011.
Since IC7011 is not used in cases other than the RGB3 input, the microcomputer of IC9501 makes the
PD0 terminal (Pin 9) stay at the”L” level. In this manner, the video signal, clock, sync, and DE (data
enable) output are treated with a high impedance. If the input signal is lost in the case of RGB3 input,
the SCTD output terminal (Pin 8) is turned to be at the “L” level to make the PD0 terminal stay at the “L”
level. Thus, the output is treated at high impedance. The PD0 terminal gains an input from the SCDT
output and the microcomputer output through the AND circuit at IC7012.
IC7010 stores the Plug & Play data for the panel link (RGB3 input only). The power supply and control
for IC7010 are carried out through the PL connector connected to the equipment (personal computer,
etc.).
2. Sync signal processing
(1) AD converter block (IC6502), panel link block (IC7011)
The AD converter of IC6502 is used to generate the sampling clock signal (clock on input side), based
on the horizontal sync (Pin 31) and the vertical sync (Pin 34) input from the MN connector (Pins 9 and
10). [See the foregoing Item 1. (5) AD converter block (IC6502).] A pulse output is generated from Pin
87 and fed to the latter stage, synchronized with the horizontal sync signal input. The oscillation fre-
quency of the clock can differ according to the input signal. When a VGA signal is displayed in the PC
mode, this frequency attains about 13MHz.
In the case of the RGB3 input, the outputs of clock, horizontal, and vertical sync signals are generated
from IC7011. After being applied to IC7007 (Pin 2), the clock signal is supplied from this IC7007 to each
circuit.
(2) Module-side (output side) clock generator block
The clock signal on the output side is generated at X9001 (40MHz). This signal passes through IC9005,
and is then supplied to each IC and the plasma display module.
(3) IC7503 block
1
Clock changeover
Inputs of both clock (Pin 134) on input side and another clock (Pin 135 at 40MHz) on output side
are entered in IC7503. With the CLKSEL terminal (Pin 133) under the control from the microcom-
puter, either clock is selected and output from Pin 130 to IC7506 (for dot clock). Similarly, another
output is generated from Pin 131 to IC9004.
In IC7503, a 40MHz clock signal output is directly generated (Pin 132) or a 20MHz clock output is
generated (Pin 144) after frequency division. These clock outputs are used as system clock signals
for the respective ICs.
2
Sync signal changeover (RGB3)
IC7503 receives inputs of clock, horizontal, and vertical sync signals from IC7011. During the entry
of RGB3, IC7503 performs horizontal sync phase adjustment (user menu: RGB3 adjustment). In
cases other than the RGB3 input, the horizontal sync output terminal (Pin 141) is maintained at
high impedance. The vertical sync signal input is also entered through the MN connector, and this
vertical sync signal is selected according to the input mode and output from Pin 143.
The signals of PL_MOD0 (Pin 118) and PL_MOD1 (Pin 119) intended to perform RGB3 adjustment
and the PLOTHER2 signal (Pin 140) intended to discriminate the presence of horizontal sync
signal output and to select a vertical sync signal output are generated from the I/O extension IC,
IC9503. IC9503 is controlled by SCL and SDA of the I2C bus from the microcomputer of IC9501.