NEC DLP CINEMA NC1600C, Руководство по обслуживанию

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8-35
CIRCUIT DESCRIPTION
3. DAD1000
The DAD1000 (U10, U11) is in charge of bias voltage feeding and pixel mirror control for the DMD.
Voltage supplies are only the outputs from VOFFSET of U10.
Mirror control (reset waveform) is carried out for 15 lines (even numbers out of 0~29) from U10 and 15 lines
(odd numbers out of 0~29) from U11, 30 in all.
To drive the DMD in Single ASIC mode, this system uses only the C and D ports out of four ports of A~D in all.
Therefore, 64*2 pins for the A and B ports are not used.
4. RLDRAM (U7, U8)
The RLDRAM (U7, U8) employs two pieces of 288M (8M*36 bits) for the main memory. The upper section
(Addr0~35) is shouldered by U7, while the lower section (Addr36~71) is shouldered by U8.
This device calls for the following four types of power supplies.
VEXT feeds the 2.5V power through 02 (Power FET).
VDD and VDDC feed the 1.8V power converted at U5.
VREF and VTT feed the power of two systems where the 5V output from the DAD1000 is converted to 0.9V
by U9.
U9 (TPS51100DG0) is an optimized device for DDR Memory Termination.
VEXT : Main 2.5V
VDD : Core 1.8V
VDDQ : I/O 1.8V
VREF : Reference 0.9V
VTT : Trmination 0.9V
5. Power
5-1. Power input
The power of three systems is fed through the pins of J3 specified below.
12V : #3
for DAD1000, DMD (12V > 26V)
3.3V : #5
for FPGA Core (3.3V > 1.2V), DMD,
FPGA I/O, RLDRAM (3.3V > 1.8V)
2.5V : #1, #7
for FPGA I/O, OSC
5-2. Voltage converter
The DC-DC converter (U4 / TPS54610PWP) generates the 1.2V power from 3.3V for the core power
supply of FPGA.
The DC-DC converter (U5 / TPS54610PWP) generates the 1.8V power from 3.3V for the I/O power
supply of FPGA.
6. Status LED
LED “D8” provides the status information about the system.
Upon normal completion of configuration, LED is lit in green. In the case of incompletion, the LED is not lit.