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3-1
3
Carrier Board PCB Layout
Guidelines
Use the guidelines in this chapter to help you arrange the I/O signals you implement in your
carrier board design.
Impedance-Controlled Signaling
Use the following guidelines for implementing impedance for all I/O signals:
•
All signals connected to the sbRIO-9651 SOM must use impedance-controlled traces.
Refer to the sections of this document listed in Table 3-1 for information about impedance
requirements.
•
Trace geometry to meet impedance requirements vary depending on your specific carrier
board PCB stack-up. Collaborate with your vendor to match impedance requirements,
stack-up, and trace geometry appropriate for your application.
•
To properly maintain trace impedance and avoid discontinuities, you cannot route traces
over gaps in the reference plane. Use stitching vias and capacitors when appropriate near
layer changes to provide a transient return path between reference planes.
Table 3-1.
Impedance Requirements Resources
Impedance Requirement
Resource
General requirements for single-ended
signals
Single-Ended Signal Best Practices
section of this
chapter
General requirements for differential
signals
Differential Signal Best Practices
section of this
chapter
Signal-specific requirements
Signal-specific sections in Chapter 1,