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2-2
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Chapter 2
User-Defined FPGA Signals
GBE1 Signal Definitions on the Reference Carrier
Board
Table 2-1 describes the GBE1 pins and signals on the sbRIO-9651 SOM connector used to
implement a secondary Ethernet port on the reference carrier board.
Table 2-1.
GBE1 Signal Definitions
Signal Name
Pin #
*
DIO Signal on
Reference
Carrier Board
Direction
†
Description
TX Signals
GBE1_GMII_GTX_CLK
192
DIO_62_N
O
Gigabit transmit
clock.
GBE1_MII_TX_CLK
207
DIO_60_SRCC
I
10/100 transmit
clock.
GBE1_GMII_TX_EN
215
DIO_60_N
O
Transmit
enable.
GBE1_GMII_TX_ER
183
DIO_59
O
Transmit error.
GBE1_GMII_TX_D0
GBE1_GMII_TX_D1
GBE1_GMII_TX_D2
GBE1_GMII_TX_D3
GBE1_GMII_TX_D4
GBE1_GMII_TX_D5
GBE1_GMII_TX_D6
GBE1_GMII_TX_D7
235
227
211
203
187
179
234
242
DIO_49_N
DIO_49
DIO_48_N
DIO_48
DIO_47_N
DIO_47
DIO_46_N
DIO_46
O
Transmit data
bus.
RX Signals
GBE1_GMII_RX_CLK
231
DIO_61_MRCC
I
Receive clock.
GBE1_GMII_RX_DV
200
DIO_62_MRCC
I
Receive data
valid.
GBE1_GMII_RX_ER
239
DIO_61_N
I
Receive error.