2-4
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Chapter 2
User-Defined FPGA Signals
GBE1 Reference Schematic
Figure 2-1 shows a schematic design for the GBE1 implementation on the reference carrier
board.
GBE1_SPEED_LEDg
GBE1_SPEED_LEDy
126
‡
118
‡
DIO_33
DIO_33_N
O
Speed LED
signals:
Yellow = 1000
Green = 100
Off = 10
*
When you use the sbRIO CLIP Generator to enable secondary Ethernet, you must use the pins listed in
this table. If you do not enable secondary Ethernet, you can use these pins for other FPGA DIO.
†
I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the
sbRIO CLIP Generator.
‡
You can use any available FPGA DIO lines to implement these signals. In NI-RIO Device Drivers
February 2015 or later, you can use the sbRIO CLIP Generator to assign FPGA DIO to these signals.
Table 2-1.
GBE1 Signal Definitions (Continued)
Signal Name
Pin #
*
DIO Signal on
Reference
Carrier Board
Direction
†
Description