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Chapter 1
Fixed Behavior Signals
USB1 Host Implementation on the Reference Carrier
Board
Figure 1-3 shows a schematic design for the USB1 Host implementation on the reference carrier
board.
Figure 1-3.
USB1 Host Reference Schematic
USB1_CPEN
50
O
LVTTL
USB1 over-current
protection enable.
USB1_VBUS
58
I
5 V tolerant
voltage sense
USB1 VBUS input.
Allows USB PHY to
sense if VBUS is present
on the connector.
*
I/O direction is with respect to the sbRIO-9651 SOM.
Table 1-8.
USB1 Host Signal Definitions (Continued)
Signal Name
Dedicated
SOM Pin #
Direction
*
I/O
Standard
Description
U
S
B1_DN
U
S
B1_DP
U
S
B1_CPEN
U
S
B1_VBU
S
4
2
3
1
L
3
DLW 21
S
_900
3
2
1
D+
D–
U18
TPD2EU
S
B
3
0
GND
1
2
R86
4.7 K
0.5%
1/16 W
R92
1 k
0.5%
2
1
–
C67
100 UF
6.
3
V
20%
1
2
C57
0.1 UF
10%
16 V
4
3
5
2
1
7
6
U20
IN
EN
ILIM
OUT
FAULT~
GND
PAD
TP
S
255
3
1
2
2
1
R89
2
3
.2 K
0.5%
1/16 W
R85
4.7 K
0.5%
1/16 W
4
5
6
1
2
3
J10
VCC
–DAT1
+DAT1
S
HLD1
S
HLD2
GND
U
S
B_A
2
2
2
2
+5 V
+5 V
2
1
R82
0 5%
1/16 W
2
1
R79
0 5%
1/16 W
1
2
R9
3
1 K
.5%
1
2
2
1
C61
0.01 UF
100 V
10%
1
2
C62
22 UF
25 V
10%
0.1 UF 10%
50 V
C20
3
1
2
POPULATION OPTION
S
FOR EMC/EMI
NOT POPULATED
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