© National Instruments
|
2-1
2
User-Defined FPGA Signals
The sbRIO-9651 SOM connector provides several banks of FPGA pins that you can configure
for purposes specific to your application. In addition to FPGA Digital I/O (DIO), you can use
these pins to implement the following run-time peripheral interfaces:
•
Secondary Ethernet (GBE1)
•
Additional RS-232 (Serial2, Serial3, Serial4)
•
RS-485 (Serial5, Serial6)
•
CAN (CAN0, CAN1)
The reference carrier board included with the sbRIO-9651 SOM development kit shows an
example of how to implement these signals. Refer to the specific sections in this chapter for more
information about how the reference carrier board implements each signal.
Note
To read or write to this I/O from a LabVIEW project, you must use the
sbRIO CLIP Generator application to create a socketed component-level IP (CLIP)
that defines the I/O configuration of the sbRIO-9651 SOM to use in your application.
Refer to the
Getting Started with the NI sbRIO-9651 in LabVIEW
topic in the
LabVIEW Help
for more information about creating a CLIP.
Tip
When you create your own CLIP, you must compile your FPGA VI and
download it to the flash of the sbRIO-9651 SOM. This ensures that the driver for
each enabled peripheral can load properly at boot time. Refer to the
Downloading an
FPGA VI to the Flash Memory of an FPGA Target
topic in the
LabVIEW Help
(FPGA Module)
for more information.
Secondary Ethernet (GBE1)
You must use specific FPGA pins to implement a secondary Ethernet port due to the strict timing
requirements across semiconductor process and temperature variations.
The reference carrier board implements one secondary Ethernet port (GBE1) in addition to the
primary Ethernet port. Refer to the
section of Chapter 1,
, for more information about implementing a primary Ethernet port.
Note
The sbRIO CLIP Generator enforces the selection of specific FPGA pins
when you implement a secondary Ethernet port.