National Instruments NI PXI-665 Series, Руководство пользователя

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NI PXI-665x User Manual
Input threshold
Voltage level ............................................. 0 to 4.3 V, software-selectable
Voltage resolution ..................................... 16.8 mV (8 bits)
Error.......................................................... ±40 mV
Hysteresis.......................................................... 50 mV
Asynchronous delay, t
pd
PFI <0..5> to
PXI_TRIG <0..7> output.......................... 15 ns to 23 ns, typical
PFI <0..5> to
PXI_STAR <0..12> output ....................... 10 ns to 19 ns, typical
Synchronized trigger input setup time, t
setup
1
... 11.2 ns, typical
Synchronized trigger input hold time, t
hold
1 ..... -10.8 ns, typical
Output Characteristics
Frequency range ............................................... DC to 105 MHz
Output impedance............................................. 50
Ω , nominal
Output coupling ................................................ DC
Voltage level ..................................................... 0 to 1.6 V into 50
Ω ;
0 to 3.3 V into open circuit, typical
Absolute maximum applied voltage
2
................ ±5.25 V, max
Output current................................................... ±48 mA, max
Synchronized trigger clock
to out time, t
CtoQ
1
............................................. 8.4 ns, typical
Output-to-output skew, synchronous ................ 500 ps, typical
PXI_STAR Trigger Characteristics
PXI_STAR <0..12> to
PXI_STAR <0..12> output skew
at NI PXI-665
x
backplane connector 3 .............. 300 ps, typical
Asynchronous delays, t
pd
PXI_STAR <0..12> to
PFI <0..5> output...................................... 7 to 11 ns, typical
PXI_STAR <0..12> to
PXI_TRIG <0..7> output.......................... 13 to 19 ns, typical
1 Relative to PXI_CLK10.
2
Stresses beyond those listed can cause permanent damage to the device. Exposure to absolute maximum
rated conditions for extended periods of time can affect device reliability. Functional operation of the
device outside the conditions indicated in the operational parts of the specifications is not implied.
3 This specification applies to all synchronous routes to the PXI_Star lines, as well as asynchronous routes
from the PFI inputs to the PXI_Star lines.