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3-15
Using Front Panel PFIs As Inputs
The front-panel PFIs can receive external signals from 0 to +5 V. The input impedance of PFI
inputs can be programmatically set to 10 k
Ω
or 50
Ω
, to match the cable impedance and
minimize reflections.
Note
Terminating the signals with a 50
Ω
resistance is recommended when the
source is another NI PXI-665
x
or any other source with a 50
Ω
output.
The voltage thresholds for the front-panel PFI inputs are programmable. The input signal is
generated by comparing the input voltage on the PFI connectors to the voltage output of
software-programmable DACs. The thresholds for the PFI lines are individually programmable,
which is useful if you are importing signals from multiple sources with different voltage swings.
The front panel PFI inputs can be routed to any PXI star triggers, PXI/RTSI triggers, or other
front panel PFI outputs.
Using Front Panel PFIs As Outputs
The front panel PFI outputs are +3.3 V drivers with 50
Ω
output impedance. The outputs can
drive high-impedance loads or 50
Ω
loads, such as a 50
Ω
coaxial cable with a 50
Ω
receiver.
When driving a high-impedance load, the receiver sees a +3.3V signal. When driving a 50
Ω
load the receiver sees a 1.6 V step—a +3.3 V step split across the 50
Ω
resistors at the
source and the destination. This cable configuration is the recommended setup to minimize
reflections.
You can independently select the output signal source for each PFI line from one of the following
sources:
•
Another PFI <0..5>
•
PXI/RTSI triggers <0..7> (PXI_TRIG <0..7>)
•
PXI_STAR <0..12>
•
Global software trigger
•
PFI synchronization clock
The PFI synchronization clock may be any of the following signals:
•
DDS clock
•
PXI_CLK10
•
PFI 0 Input
•
Any of the previously listed signals divided by the first frequency divider (2
n
, up to 512)
•
Any of the previously listed signals divided by the second frequency divider (2
m
, up to 512)
Refer to the
section for more information on the synchronization
clock.