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3-21
window around the synchronization clock edge, one of the destinations might go to the new logic
level while the other destination might remain at the old logic level and change when the next
synchronization clock edge occurs.
Figure 3-12.
Synchronous Routing Uncertainty with Setup-and-Hold Violation
Therefore, if your application requires that the trigger arrive at the multiple destinations
simultaneously, you must ensure that the input is stable within the setup and hold window around
the synchronization clock edge. For more information and possible methods to ensure this
requirement is met, go to
ni.com/info
and enter Info Code
SyncTriggerRouting
.
Possible sources for synchronous routing include the following sources:
•
Any front panel PFI pin
•
Any PXI star trigger line (PXI_STAR <0..12>)
•
Any PXI/RTSI trigger line (PXI_TRIG <0..7>)
•
Global software trigger
•
The synchronization clock itself
The destination of a synchronous routing operation on the NI PXI-665
x
can be any of the
following lines:
•
Any front panel PFI pin (PFI <0..5)
•
Any PXI star trigger line (PXI_STAR <0..12>)
•
Any PXI/RTSI trigger line (PXI_TRIG <0..7>)
The synchronization clock for a synchronous route can be any of the following signals:
•
10 MHz PXI backplane clock signal
•
DDS clock on the NI PXI-6653 or NI PXI-6652
•
Front panel PFI 0 Input
•
One of two “divided copies” of any of the previously listed three signals. The NI PXI-665
x
includes two clock-divider circuits that can divide the synchronization clock signals by any
power of 2 up to 512.
S
ynchroniz
a
tion CLK
Trigger O
u
tp
u
t 2
Trigger O
u
p
u
t 1
Trigger Inp
u
t
t
s
et
u
p
t
hold
t
CtoQ
t
CtoQ