NI 5762R User Guide and Specifications
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The NI 5762 ships with socketed CLIP items that are used to add module I/O to the LabVIEW project.
The NI 5762 ships with the following CLIP items:
•
NI 5762 Multiple Sample CLIP
—This CLIP generates two samples per clock cycle at a clock rate
that is half the sample rate. The default sample rate is 250 MHz, which sets the default clock rate
for this CLIP at 125 MHz. You can set a lower sample rate by using an external Sample clock. This
CLIP provides access to two analog input channels, eight DIO lines, four PFI lines, and an input
clock selector that can be configured to use one of the following settings:
–
Internal Sample clock
–
Internal Sample clock locked to an external Reference clock through Sync Clock
(IoModSyncClk)
–
Internal Sample clock locked to an external Reference clock through the CLK IN connector
–
External Sample clock through the CLK IN connector
This CLIP also contains an engine to program the clock chip and ADCs, either through predetermined
settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced
setup. Additionally, this CLIP provides an I2C interface to access a user EEPROM and a temperature
sensor. In the LabVIEW FPGA Module, each analog signal uses a signed I16 data type. The DIO signals
are grouped into two ports of four signals each and are accessed using a U8 data type and Boolean write
enable signal. The four PFI signals are accessed individually using Boolean controls.
The NI 5762 Multiple Sample CLIP is the default CLIP.
•
NI 5762 Single Sample CLIP
—This CLIP generates one sample per clock cycle at a default
sample rate of 250 MHz. You can set a lower sample rate by using an external Sample clock. This
CLIP provides access to two analog input channels, eight digital input/output lines, four PFI lines,
and an input clock selector that can be configured to use one of the following settings:
–
Internal Sample clock
–
Internal Sample clock locked to an external Reference clock through Sync Clock
(IoModSyncClk)
–
Internal Sample clock locked to an external Reference clock through the CLK IN connector
–
External Sample clock through the CLK IN connector
This CLIP also contains an engine to program the clock chip and ADCs, either through predetermined
settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced
setup. Additionally, this CLIP provides an I2C interface to access a user EEPROM and a temperature
sensor. The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data
type and Boolean write enable signal. The four PFI signals are accessed individually using Boolean
controls.
Refer to the
NI FlexRIO Help
for more information about NI FlexRIO CLIP items, configuring the
NI 5762 with a socketed CLIP, and a list of available socketed CLIP signals.
