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National Instruments Corporation
9
NI 5762R User Guide and Specifications
Cables
Use any shielded 50
Ω
coaxial cable with an SMA plug end to connect to the AI 0, AI 1, EXT TRIG,
and CLK IN connectors on the NI 5762 front panel.
Use any HDMI cable with the two provided cable ferrites to connect to the digital I/O and PFI signals
on the AUX I/O connector. Refer to the
Appendix: Installing EMI Controls
section for more information
about attaching cable ferrites.
For more information about connecting I/O signals on your device, refer to the
section of
this document.
Clocking
The NI 5762 clocks control the sample rate and other timing functions on the device. Table 4 contains
information about the possible NI 5762 clock resources. For more clocking information, refer to the
section of the specifications.
Using Your NI 5762R with a LabVIEW FPGA Example VI
Note
You must install the software before running this example. Refer to the
NI FlexRIO FPGA
Module Installation Guide and Specifications
for more information about installing your software.
The NI FlexRIO Adapter Module Support software includes a variety of example projects to help get
you started creating your LabVIEW FPGA application. This section explains how to use an existing
LabVIEW FPGA example project to generate and acquire samples with the NI 5762R. This example
requires at least one SMA cable for connecting signals to your NI 5762R.
Note
The examples available for your device are dependent on the version of the software and driver
you are using. For more information about which software versions are compatible with your device,
visit
ni.com/info
and enter
rdsoftwareversion
as the Info Code.
Each NI 5762R example project includes the following components:
•
A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware. This
VI is referred to as the FPGA Target VI.
•
A VI that runs on Windows that interacts with the LabVIEW FPGA VI. This VI is referred to as
the Host VI.
Table 4.
NI 5762 Clock Sources
Clock
Frequency
Description
Internal Clock
PLL Off
250 MHz
The internal VCXO acts as a free-running clock.
Internal Clock
PLL On
(IoModSyncClk)
250 MHz
The internal VCXO locks to PXI_CLK10 through Sync Clock
(IoModSyncClk), which is provided only through the backplane
of NI PXIe-796
x
R devices.
Internal Clock
PLL On
(CLK IN)
250 MHz
The internal VCXO locks to an external Reference clock
(10 MHz), which is provided through the CLK IN front panel
connector.
External Clock
(CLK IN)
150 MHz to 250 MHz
An external Sample clock can be provided through the CLK IN
front panel connector.
