©
National Instruments Corporation
13
NI 5762R User Guide and Specifications
25. Save and close the VI.
26. Save the project.
Creating a Host VI
1.
In the
Project Explorer
window, right-click
My Computer
and select
New»VI
. A blank VI opens.
2.
Select
Window»Show Block Diagram
to open the VI block diagram.
3.
Place the
Open FPGA VI Reference function
, located on the
FPGA Interface
palette, on the
block diagram.
4.
Right-click the
Open FPGA VI Reference function
and select
Configure Open FPGA VI
Reference
.
5.
In the
Configure Open FPGA VI Reference
dialog box, select
VI
in the
Open
section.
6.
In the
Select VI
dialog box that opens, select
5762SampleAcq (FPGA).vi
under your device and
click
OK
.
7.
Click
OK
in the
Configure Open FPGA VI Reference
dialog box. The target name appears under
the
Open FPGA VI Reference
function in the block diagram.
8.
Add a While Loop to the block diagram. Place it to the right of the
Open FPGA VI Reference
function.
9.
Right-click the conditional terminal inside the While Loop, and select
Create Control
to create a
STOP button on the VI front panel window.
10. Add the
Read/Write Control function
, located on the
FPGA Interface
palette, inside the
While Loop.
11. Wire the
FPGA VI Reference Out
output terminal of the
Open FPGA VI Reference function
to
the
FPGA VI Reference In input terminal on the
Read/Write Control
function
.
12. Wire the
error out
terminal of the
Open FPGA VI Reference function
to the
error in
control of
the
Read/Write Control function
.
13. Configure the Read/Write Control function by clicking the terminal section labeled
Unselected
,
and selecting
IO Module/AI 0 Data N
.
14. Add the
IO Module/AI 0 Data N-1
I/O item to the Read/Write Control function by clicking the
handle on the bottom of the control node with the Positioning tool and dragging the edge down.
15. Wire indicators to the output terminals of the
IO Module\
AI 0 Data N
and
IO Module\
AI 0 Data N-1
nodes.
16. Add the
Close FPGA VI Reference function
, located on the
FPGA Interface
palette, to the right
of the While Loop on the block diagram.
17. Wire the
FPGA VI Reference Out
terminal of the Read/Write Control
function
to the
FPGA VI
Reference In terminal of the Close FPGA VI Reference function
.
