Motorola MVME2603-1121A, Инструкция по установке и эксплуатации

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Hardware Preparation and Installation
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address ranges indicated in Chapter 2. D8 and/or D16 devices in
the system must be handled by the PowerPCª processor software.
Refer to the memory maps in Chapter 2.
The MVME2603/2604 contains shared onboard DRAM (and,
optionally, secondary cache memory) whose base address is
software-selectable. Both the onboard processor and offboard
VMEbus devices see this local DRAM at base physical address
$00000000, as programmed by the firmware. This may be changed
via software to any other base address. Refer to the
MVME2600
Series Single Board Computer Programmer's Reference Guide for more
information.
If the MVME2603/2604 tries to access offboard resources in a
nonexistent location and is not system controller, and if the system
does not have a global bus timeout, the MVME2603/2604 waits
forever for the VMEbus cycle to complete. This will cause the
system to lock up. There is only one situation in which the system
might lack this global bus timeout: when the MVME2603/2604 is
not the system controller and there is no global bus timeout
elsewhere in the system.
Multiple MVME2603/2604s may be installed in a single VME
chassis. In general, hardware multiprocessor features are
supported.
Other MPUs on the VMEbus can interrupt, disable, communicate
with, and determine the operational status of the processor(s). One
register of the GCSR (global control/status register) set includes
four bits that function as location monitors to allow one
MVME2603/2604 processor to broadcast a signal to any other
MVME2603/2604 processors. All eight registers are accessible
from any local processor as well as from the VMEbus.
The MVME2603/2604 VMEmodule draws +5Vdc, +12Vdc, and
Ð12Vdc power from the VMEbus backplane through connectors P1
and P2. The 3.3Vdc and the processor core voltage power is
supplied by the on-board +5Vdc.