Motorola MVME2603-1121A, Инструкция по установке и эксплуатации

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Memory Maps
2-6
2
Notes 1. Default map for PCI/ISA I/O space. Allows software to
determine whether the system is MPC105-based or
Falcon/Raven-based by examining either the PHB Device ID or
the CPU Type register.
2. The first 1MB of ROM/Flash bank A (soldered 4MB or 8MB
ROM/Flash) appears in this range after a reset if the rom_b_rv
control bit in the FalconÕs ROM B Base/Size register is cleared.
If the
rom_b_rv control bit is set, this address range maps to
ROM/Flash bank B (socketed 1MB ROM/Flash).
For detailed processor memory maps, including suggested CHRP-
and PREP-compatible memory maps, refer to the
MVME2600 Series
Single Board Computer ProgrammerÕs Reference Guide (part number
V2600A/PG).
PCI Local Bus Memory Map
The PCI memory map is controlled by the Raven MPU/PCI bus
bridge controller ASIC and by the Universe PCI/VME bus bridge
ASIC. The Raven and Universe devices adjust system mapping to
suit a given application via programmable map decoder registers.
No default PCI memory map exists. Resetting the system turns the
PCI map decoders off, and they must be reprogrammed in software
for the intended application.
Table 2-1. Processor Default View of the Memory Map
Processor Address
Size DeÞnition Notes
Start End
00000000 7FFFFFFF 2GB Not Mapped
80000000 8001FFFF 128KB PCI/ISA I/O Space 1
80020000 FEF7FFFF 2GB-16MB-640KB Not Mapped
FEF80000 FEF8FFFF 64KB Falcon Registers
FEF90000 FEFEFFFF 384KB Not Mapped
FEFF0000 FEFFFFFF 64KB Raven Registers
FF000000 FFEFFFFF 15MB Not Mapped
FFF00000 FFFFFFFF 1MB ROM/Flash Bank A or Bank B 2