< Dual-In-Line Package Intelligent Power Module >
Series Application note
Publication Date: September 2016
34
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
,AIN
Fo
V
NC
(Logic)
DIPIPM
MCU/DSP
10k
Ω
5V line
3.3k
Ω (min)
Fig.3-1-6 Control input connection
(note)
(1) The RC coupling (parts shown as broken line) at each input depends on user’s PWM control strategy and the wiring
impedance of the printed circuit board.
(2) The DIPIPM signal input section integrates a 3.3k
Ω(min) pull-down resistor. Therefore, when using an external
filtering resistor, please be careful to the signal voltage drop at input terminal.
Table 3-1-2 Allowable minimum input pulse width
Item
Symbol
Condition
Min. value
Unit
Allowable
minimum input
pulse width
PWIN(on) Up to 1.7 times of rated current
1.5
μs
PWIN(off)
0
≤V
CC
≤800V(for 1200V series) or
0
≤V
CC
≤350V(for 600V series),
13.5
≤V
D
≤16.5V, 13.0≤V
DB
≤18.5V,
-20
°
C
≤Tc≤100
°
C,
N line wiring inductance less than 10nH
Up to rated
current
3
From rated
current to 1.7
times of rated
current
3.5
(note)
(1)
Input signal with ON pulse width less than PWIN(on) might make no response.
(2)
IPM might make no response or delayed response for the input OFF signal with pulse width less than PWIN(off).
(Delay occurs for p-side only.) Please refer the following Fig.3-1-7 of delayed response.
Fig.3-1-7 Delayed response of output operation with inputting less than PWIN(OFF) for P-side
P Side Control Input
Internal IGBT Gate
Output Current Ic
t1
t2
Real line
: off pulse width>PWIN(off); turn on time t1
Broken line : off pulse width<PWIN(off); turn on time t2
(t1:Normal switching time)