< Dual-In-Line Package Intelligent Power Module >
Series Application note
Publication Date: September 2016
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CHAPTER 3 : SYSTEM APPLICATION GUIDANCE
3.1 Application guidance
This chapter states the application method and interface circuit design hints.
3.1.1 System connection
Fig.3-1-1 System block diagram (Example)
C1: Electrolytic type with good temperature and frequency characteristics
(note) The capacitance also depends on the PWM
control strategy of the application system
C2: 0.01
μ-2μF ceramic capacitor with good temperature,
frequency and DC bias characteristics
C3: 0.1
μ-0.22μF Film capacitor (for snubber)
D1: Zener diode 24V/1W for surge absorber
Z : Surge absorber
C : AC filter(ceramic capacitor 2.2n -6.5nF)
(Common-mode noise filter)
Drive circuit
UV lockout
circuit
Level shift
Input signal
conditioning
Drive circuit
Level shift
Input signal
conditioning
Drive circuit
Level shift
Input signal
conditioning
Drive circuit
UV lockout
circuit
Fo Logic
Input signal
conditioning
P-side input
Fo
Fo output
V
NC
N1
N
CIN
V
NC
V
D
(15V line)
C1
C2
N-side input
Inrush
limiting circuit
P
V
U
W
M
AC output
N-side IGBTs
P-side IGBTs
AC line input
(CIB type)
Protection
circuit
(SC)
D1
C3
C1
C2
D1
UV lockout
circuit
UV lockout
circuit
CFo
Drive circuit
UV lockout
circuit
Brake input
Temp. output
V
OT
B
Input signal
conditioning
Braking
resistor
N(B)
Brake IGBT
Brake Di
Z C
P
N1
R
S
T