DMU380ZA Series
User’s Manual
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Doc# 7430-3810 Rev. 02
Page 36
Table 20 DMU380ZA Burst-Mode Output Registers
Register Name
Register Address
Description
STATUS
0x3C
System Status
X_RATE
0x04
Rate Sensor Output (X-Axis)
Y_RATE
0x06
Rate Sensor Output (Y-Axis)
Z_RATE
0x08
Rate Sensor Output (Z-Axis)
X_ACCEL
0x0A
Accelerometer Output (X-Axis)
Y_ACCEL
0x0C
Accelerometer Output (Y-Axis)
Z_ACCEL
0x0E
Accelerometer Output (Z-Axis)
BOARD_TEMP
0x18
System Temperature
Burst-mode begins when the master requests a read from a burst-mode data-packet (i.e.
0x3E). Eight additional SPI cycles complete the read (one for each word in the standard
data-packet). Figure 11 illustrates the burst-mode sequence. Note: if the incorrect
number of SPI cycles follow the burst-mode command, the SPI transfer will either
complete early or remain in burst-mode; subsequent reads/writes will be out of sync with
the SPI transfer cycle of the DMU380ZA.
Figure 11 Multiple Register Read via Burst-Mode
Operational notes:
1.
When combining polled and burst reads, use only single-register polled-reads.
2.
Burst-mode reads for other data-packets are performed in a manner similar to the
standard packet. The only deviation from the method described above is the register
address and the subsequent number of data words, listed in Table 20.
3.
Care must be taken when switching between data-packets as values returned during
the first burst-read of a new packet are invalid. A single read-cycle is needed to
populate the internal burst-mode register; subsequent reads from the same packet
contain valid information.
4.
During a burst read, the chip-select line (nSS) can be controlled in one of two ways:
Toggle nSS in between each of the 16-bit words (as shown in Figure 11).
Set and hold nSS low during the entire read. After the transfer is complete, set
chip-select high.
nSS
CLK
MOSI
MISO
0x3E00
0x0000
0x0000
0x0000
N/A
STATUS
X_RATE
BOARD_
TEMP