Maxim Integrated MAX32660, Руководство пользователя

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MAX32660 User Guide
Maxim Integrated Page 169 of 195
SPI0 has four Wakeup (WAKE) sources that can wake the core from SLEEP mode when the WAKE event occurs. The
following WAKE events are supported:
•
Wake on RX FIFO Full
•
Wake on TX FIFO Empty
•
Wake on RX FIFO Level crossed
•
Wake on TX FIFO Level crossed
13.4 SPI0 Registers
The SPI0 base peripheral address is 0x4004 6000. Refer to Table 3-1: APB Peripheral Base Address Map for the addresses of
all APB mapped peripherals.
Table 13-5: SPI0 Master Register Addresses and Descriptions
Offset Register Name Access Description
[0x0000] SPI0_DATA R/W SPI FIFO Data Register
[0x0004] SPI0_CTRL0 R/W SPI Master Signals Control Register
[0x0008] SPI0_CTRL1 R/W SPI Transmit Packet Size Register
[0x000C] SPI0_CTRL2 R/W SPI Static Configuration Register
[0x0010] SPI0_SS_TIME R/W SPI Slave Select Timing Register
[0x0014] SPI0_CLK_CFG R/W SPI Master Clock Configuration Register
[0x001C] SPI0_DMA R/W SPI DMA Control Register
[0x0020] SPI0_INT_FL R/W1O SPI Interrupt Status Flags Register
[0x0024] SPI0_INT_EN R/W SPI Interrupt Enable Register
[0x0028] SPI0_WAKE_FL R/W1O SPI Wakeup Status Flags Register
[0x002C] SPI0_WAKE_EN R/W SPI Wakeup Enable Register
[0x0030] SPI0_STAT RO SPI Active Status Register
13.4.1 SPI0 Register Details
Table 13-6: SPI FIFO Data Registers
SPIn FIFO Data Register SPI0_DATA [0x0000]
Bits Name Access Reset Description
31:0 - R/W 0
SPI FIFO Data Register
Reading from this register dequeues data from the receive FIFO.
Writes to this register queues data to the transmit FIFO.
Reads and writes with this register are in 1-byte, 2-byte, or 4-byte widths only.
Table 13-7: SPI Master Signals Control Registers
SPI Master Signals Control Register SPI0_CTRL0 [0x0004]
Bits Name Access Reset Description
31:20 - R/W 0
Reserved for Future Use
Do not modify this field.