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MAX32660 User Guide
Maxim Integrated Page 139 of 195
12.7 I
2
C TX FIFO and RX FIFO Management
There are separate transmit and receive FIFOs, TX FIFO and RX FIFO. Both are accessed using the FIFO Data register
I2Cn_FIFO . Writes to this register enqueue data into the TX FIFO. Writes to a full TX FIFO have no effect. Reads from
I2Cn_FIFO dequeue data from the RX FIFO. Reads from an empty RX FIFO returns 0xFF.
The TX and RX FIFO will only read or write one byte at a time. Transactions larger than 8 bits can still be performed,
however. A 16- or 32-bit write to the TX FIFO stores just the lowest 8 bits of the write data. A 16- or 32-bit read from the RX
will hav th vali ata in th l w st 8 bits an 0’s in th upp r bits. n any cas , th X an X s will nly acc pt 8
bits for a read or a write.
Both the RX FIFO and TX FIFO are flushed when the I
2
C port is disabled by clearing I2Cn_CTRL0 . i2cen = 0.
The TX FIFO and RX FIFO can be flushed by setting the Transmit FIFO Flush bit ( I2Cn_TXCTRL0 . txfsh = 1) or the Receive FIFO
Flush bit ( I2Cn_RXCTRL0 . rxfsh = 1), respectively.
12.7.1 Transmit Lockout
Under certain conditions the TX FIFO is automatically locked by hardware and flushed so stale data is not unintentionally
transmitted. The TX FIFO is automatically flushed, and writes are locked out under the following conditions:
•
General Call Address match and TX FIFO Preloading is disabled
•
Slave Address match and TX FIFO Preloading is disabled
•
Operating as a slave transmitter, and a NACK is received.
•
Any of the following interrupts: Arbitration Error, Timeout Error, Master Mode Address NACK, Data NACK Error,
Start Error, and STOP Condition Detected.
When the above conditions occur, the TX FIFO is flushed so stale data is not unintentionally transmitted. In addition, the
Transmit Lockout Flag is set (
I2Cn_INTFL0 . txloi = 1) and writes to the TX FIFO are ignored until firmware acknowledges the
external event by clearing I2Cn_INTFL0 .txloi.
Flushing the TX FIFO on Slave Address Match or General Call Match can be disabled using the Transmit FIFO Preload bit
(
I2Cn_TXCTRL0 . txpreld ). Setting this bit allows applications to preload the Transmit FIFO prior to a Slave Address Match.
This can be combined with Slave Clock Stretching disabled ( I2Cn_CTRL0 .sclstrd = 0) to maximize the chance of completing a
transmit operation without a transmit underflow error.
12.8 Interactive Receive Mode (IRXM)
In some situations, this I
2
C might want to inspect and respond to each byte of received data. In this case, Interactive
Receive Mode can be used. Interactive Receive Mode is enabled by setting I2Cn_CTRL0 . irxm = 1. If Interactive Receive Mode
is enabled, it must occur before any I
2
C transfer is initiated.
When Interactive Receive Mode (IRXM) is enabled, after every data byte received the I
2
C peripheral automatically holds SCL
low before the ACK bit. Additionally, after the 8th SCL falling edge, the I
2
C peripheral sets the IRXM Interrupt Status Flag
( I2Cn_INTFL0 . irxmi = 1). Application firmware must read the data and generate a response (ACK or NACK) by setting the
IRXM Acknowledge ( I2Cn_CTRL0 .ack ) bit accordingly. Send an ACK by clearing the I2Cn_CTRL0 . ack bit to 0. Send a NACK by
setting the I2Cn_CTRL0 . ack bit to 1.
After setting the I2Cn_CTRL0 . ack bit, clear the IRXM interrupt flag. Write 1 to I2Cn_INTFL0 .irxmi to clear the interrupt flag.
When the IRXM interrupt flag is cleared, the I
2
C peripheral hardware releases the SCL line and sends the I2Cn_CTRL0 .ack on
the SDA line. For both master and slave operations, SCL is released only after the necessary SCL low time requirement is
satisfied to conform with
t
su;dat
timing.