Maxim Integrated MAX32660, Руководство пользователя

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MAX32660 User Guide
Maxim Integrated Page 152 of 195
I
2
C Interrupt Enable 1 Register I2Cn_INTEN1 [0x0014]
Bits Name Access Reset Description
0 rxofie R/W 0
Slave Mode RX FIFO Overflow Interrupt Enable
In slave mode operation, set this field to enable the RX FIFO overflow interrupt.
0: Interrupt disabled.
1: Interrupt enabled.
Table 12-10: I
2
C FIFO Length Registers
I 2 C FIFO Length Register I2Cn_FIFOLEN [0x0018]
Bits Name Access Reset Description
31:16 - R/W 0
Reserved for Future Use
Do not modify this field.
15:8 txlen RO 8
TX FIFO Length
Returns the length of the TX FIFO.
8: 8-byte TX FIFO.
7:0 rxlen RO 8
RX FIFO Length
Returns the length of the RX FIFO.
8: 8-byte RX FIFO.
Table 12-11: I
2
C Receive Control Registers 0
I 2 C Receive Control Register 0 I2Cn_RXCTRL0 [0x001C]
Bits Name Access Reset Description
31:12 - R/W 0
Reserved for Future Use
Do not modify this field.
11:8 rxth R/W 0
RX FIFO Threshold Level
Set this field to the required number of bytes to trigger a RX FIFO threshold event.
When the number of bytes in the RX FIFO is equal to or greater than this field, the
hardware sets the
I2Cn_INTFL0 . rxthi bit indicating an RX FIFO threshold level event.
0: 0 bytes or more in the RX FIFO causes a threshold event.
1: 1+ bytes in the RX FIFO triggers a receive threshold event (recommended
minimum value).
…
8: RX FIFO threshold event only occurs when the RX FIFO is full.
7 rxfsh R/W1O 0
Flush RX FIFO
Write 1 to this field to initiate a RX FIFO flush, clearing all data in the RX FIFO. This
field is automatically cleared by hardware when the RX FIFO flush completes. Writing
0 has no effect.
0: RX FIFO flush complete or not active.
1: Flush the RX FIFO
6:1 - R/W 0
Reserved for Future Use
Do not modify this field.
0 dnr R/W 0
Do Not Respond
Slave mode operation only.
0: If the RX FIFO contains data and an external master requests a WRITE
transaction, respond to an address match with an ACK but NACK the subsequent
data byte(s). (No additional data is written into the RX FIFO.)
1: If the RX FIFO contains data and a master requests a WRITE transaction, do not
respond to an address match and send a NACK instead.