MAX32660 User Guide
Maxim Integrated
Page 140 of 195
While I
2
C peripheral is waiting for the application firmware to clear the
.irxmi
flag, firmware can disable
Interactive Receive Mode and, if operating as a master, load the remaining number of bytes to be received for the
transaction. This allows firmware to examine the initial bytes of a transaction, which might be a command, and then disable
Interactive Receive Mode to receive the remaining bytes in normal operation.
During IRXM, received data is not placed in the RX FIFO. Instead, the
address is repurposed to directly read the
receive shift register, bypassing the RX FIFO. Therefore, before disabling Interactive Receive Mode, firmware must first read
the data byte from
.data.
If the IRXM byte is not read, the next read from the RX FIFO returns 0xFF.
Note: Interactive Receive Mode does not apply to address bytes, only to data bytes.
Note: Interactive Receive Mode does not apply to general call address responses or START byte responses.
12.9
I
2
C DMA Control
There are independent DMA channels for each TX FIFO and each RX FIFO. DMA activity is triggered by the TX FIFO
(
txth
) and RX FIFO (
rxth
) threshold levels.
12.9.1
I
2
C Transmit DMA Burst Size
When the TX FIFO byte count (
txfifo
) is less than or equal to the TX FIFO Threshold Level
txth
,
then the DMA transfers data into the TX FIFO according to the DMA configuration. To ensure the DMA does not overflow
the TX FIFO, the DMA burst size should be set as follows:
Equation 12-3: DMA Burst Size Calculation for I
2
C Transmit
𝐷𝑀𝐴 𝐵𝑢𝑟𝑠𝑡 𝑆𝑖𝑧𝑒 = 𝑇𝑋 𝐹𝐼𝐹𝑂 𝐷𝑒𝑝𝑡ℎ − 𝐼2𝐶𝑛_𝑇𝑋𝐶𝑇𝑅𝐿0. 𝑡𝑥𝑡ℎ ≡ 8 − 𝐼2𝐶𝑛_𝑇𝑋𝐶𝑇𝑅𝐿0. 𝑡𝑥𝑡ℎ
where 0 ≤ 𝐼2𝐶𝑛_𝑇𝑋𝐶𝑇𝑅𝐿0 ≤ 7
Applications trying to avoid transmit underflow and/or clock stretching should use a smaller burst size and higher
txth
setting. This fills up the FIFO more frequently but increases internal bus traffic.
12.9.2
I
2
C Receive DMA Burst Size
When the RX FIFO count (
rxfifo
) is greater than or equal to the RX FIFO Threshold Level
rxth
,
the DMA transfers data out of the RX FIFO according to the DMA configuration. To ensure the DMA does not underflow the
RX FIFO, the DMA burst size should be set as follows:
Equation 12-4: DMA Burst Size Calculation for I
2
C Receive
𝐷𝑀𝐴 𝐵𝑢𝑟𝑠𝑡 𝑆𝑖𝑧𝑒 = 𝐼2𝐶𝑛_𝑅𝑋𝐶𝑇𝑅𝐿0. 𝑟𝑥𝑡ℎ
where 1 ≤ 𝐼2𝐶𝑛_𝑅𝑋𝐶𝑇𝑅𝐿0. 𝑟𝑥𝑡ℎ ≤ 8
Applications trying to avoid receive overflow and/or clock stretching should use a smaller burst size and lower
rxth
. This results in reading from the Receive FIFO more frequently but increases internal bus traffic.
Содержание MAX32660
Страница 4: ...MAX32660 User Guide Maxim Integrated Page 4 of 195 8 UART 84 9 Real Time Clock RTC 96 10 Timers 105...
Страница 7: ...MAX32660 User Guide Maxim Integrated Page 7 of 195 15 Trademarks 195 16 Revision History 195...
Страница 14: ...MAX32660 User Guide Maxim Integrated Page 14 of 195 Figure 2 1 MAX32660 High Level Block Diagram...
