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Technical Description
18 Revision R09, November 2016
4.2.2 Measuring and monitoring
The process monitoring is organized inside a FPGA unit. It runs independent
from the embedded Linux running in a ARM processor.
Fig. 3: Flowchart of measuring and monitoring processes inside the FPGA.
Figure 3 shows a standard measurement cycle. On completion of each measure-
ment cycle (1s), data are checked and status parameters are evaluated. If a value
is found to be out of tolerance or if a hardware error occurs, the standard meas-
urement cycle will be re-initialized.
Cyclic standard measurement is monitored by an extra routine within the FPGA.
The state of the receiver depends on the results of monitoring noise level, supply
voltage and DC-current with and without a test pulse. Due to its internal setup,
the light source is essentially characterized by the pulse repetition rate, which
may decrease because of light source aging. The pulse rate is subject to monitor-
ing. For pulse rates below 4.5 kHz, an error message is generated. The light
pulse reflection from the window panel is also analyzed to monitor the window
contamination.
All obtained values are output in an extended data telegram or inside the
NetCDF files. The standard data telegram contains approximate information
about the service code (refer to chapter 8.5).
Measurement starts (t0)
New initialization of APD
reset if necessary, trans-
Measurement and
system performance
No
Yes
Measurement stops (1s),
temperatures, signal quality,
APD voltage is checked
okay?
fer of error codes and
warnings.