LTC3810-5
29
38105fd
The internal oscillator locks to the external clock after
the second clock transition is received. When external
synchronization is detected, LTC3810-5 will operate in
forced continuous mode. If an external clock transition
is not detected for three successive periods, the internal
oscillator will revert to the frequency programmed by the
R
ON
resistor.
During the start-up phase, phase-locked loop function is
disabled. When LTC3810-5 is not in synchronization mode,
PLL/LPF pin voltage is set to around 1.215V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLL/LPF pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the V
CO
center frequency. The PLL hold-in range,
D
f
H
,
is equal to the capture range,
D
f
C:
D
f
H
=
D
f
C
= ±0.3 f
O
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLL/LPF pin. A simplified block diagram
is shown in Figure 18.
Figure 17. Equivalent Input Circuit of Error Amplifier
applicaTions inForMaTion
–
+
I
I
D1
TRACK/SS2
0.8V
V
FB2
D2
D3
38105 F17
EA2
help of Figure 17. At the input stage of the slave IC’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.8V at steady state and effectively turns off
D1. D2 and D3 will therefore conduct the same current
and offer tight matching between V
FB2
and the internal
precision 0.8V reference. In the ratiometric mode, however,
TRACK/SS equals 0.8V at steady state. D1 will divert part
of the bias current to make V
FB2
slightly lower than 0.8V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well.
For better output regulation, use the coincident
tracking mode instead of ratiometric.
Phase-Locked Loop and Frequency Synchronization
The LTC3810-5 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency f
O
. The center frequency is the operating
frequency discussed in the Operating Frequency section.
The LTC3810-5 incorporates a pulse detection circuit that
will detect a clock on the MODE/SYNC pin. In turn, it will
turn on the phase-locked loop function. The pulse width of
the clock has to be greater than 400ns and the amplitude
of the clock should be greater than 2V.
Figure 18. Phase-Locked Loop Block Diagram
DIGITAL
PHASE/
FREQUENCY
DETECTOR
MODE/SYNC
PLL/LPF
2.4V
C
LP
38105 F18
R
LP
VCO
