LTC3810-5
16
38105fd
The most important parameter in high voltage applications
is breakdown voltage BV
DSS
. Both the top and bottom
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source dur-
ing its off-time and must be chosen with the appropriate
breakdown specification. The LTC3810-5 is designed to
be used with a 4.5V to 14V gate drive supply (DRV
CC
pin)
for driving logic-level MOSFETs (V
GS(MIN)
≥ 4.5V).
For maximum efficiency, on-resistance R
DS(ON)
and input
capacitance should be minimized. Low R
DS(ON)
minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 6).
the top MOSFET but is not directly specified on MOSFET
data sheets. C
RSS
and C
OS
are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle
=
V
OUT
V
IN
Synchronous Switch Duty Cycle
=
V
IN
– V
OUT
V
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
TOP
=
V
OUT
V
IN
I
MAX
(
)
2
(
ρ
T
)R
DS(ON)
+
V
IN
2
I
MAX
2
(R
DR
)(C
MILLER
) •
1
V
CC
– V
TH(IL)
+
1
V
TH(IL)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
(f)
P
BOT
=
V
IN
– V
OUT
V
IN
(I
MAX
)
2
(
ρ
T
)R
DS(0N)
where
ρ
T
is the temperature dependency of R
DS(ON)
, R
DR
is the effective top driver resistance (approximately 2Ω at
V
GS
= V
MILLER
), V
IN
is the drain potential and the change
in drain potential in the particular application. V
TH(IL)
is
the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. C
MILLER
is the calculated capacitance using
the gate charge curve from the MOSFET data sheet and
the technique described above.
Both MOSFETs have I
2
R losses while the topside N-channel
equation incudes an additional term for transition losses,
which peak at the highest input voltage. For high input
voltage low duty cycle applications that are typical for the
LTC3810-5, transition losses are the dominate loss term and
therefore using higher R
DS(ON)
device with lower C
MILLER
usually provides the highest efficiency. The synchronous
MOSFET losses are greatest at high input voltage when
the top switch duty factor is low or during a short-circuit
when the synchronous switch is on close to 100% of
Figure 6. Gate Charge Characteristic
+
–
V
DS
V
IN
V
GS
MILLER EFFECT
Q
IN
a
b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
38105 F06
applicaTions inForMaTion
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V
DS
drain
voltage, but can be adjusted for different V
DS
voltages by
multiplying by the ratio of the application V
DS
to the curve
specified V
DS
values. A way to estimate the C
MILLER
term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V
DS
voltage specified. C
MILLER
is the most important se-
lection criteria for determining the transition loss term in
