Lexicon MPX G2, Руководство по обслуживанию

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MPX G2 Service Manual
6-16
LEXICHIP SYNCHRONIZATION. U45 uses LEXPHSAB from the Lexichip to make sure that write
accesses to the Lexichip remain stable during the Lexichip's "A" phase. It also generates LEXPHSDA,
which clocks the address bus into U55 and U56 to meet the Lexichip's address setup and hold
requirements.
BUS ARBITRATION. When U45 sees a high DEG0 from the Lexichip, which happens about half-way
through the Lexichip's word clock cycle, it asserts _ZBUSREQ. The Z80 gets off the bus and asserts
_ZBUSACK. When U45 sees this, it asserts DSP_ON_BUS, which gives the 2186 access to the system
bus. Once the 2186 has finished, it writes to an internal register in U45, which clears DSP_ON_BUS, giving
the bus back to the Z80. When the Z80 wants to sync up to the Lexichip's first instruction, it writes to a
special register in the Lexichip, which asserts _LEX_WAIT. U45 OR's this signal into the _ZBUSREQ
signal. This halts the Z80 until the Lexichip reaches the top of its instruction list.
An addressable latch was used for U66 instead of a D-flop because the control lines are likely to be set and
cleared independently. With an addressable latch, it is easier to set and clear individual bit.
SHEET 5:
Sheet 5 includes the inputs, the LCD interface, the MPX G2-specific control signals, and the pedal A/D
converter.
U75 reads the multiplexed switches from the right front panel, the encoder, and the footswitches. R646-
R649, C554 and C556 help to debounce the encoder. U71 reads other status signals.
D-flops U64 and U65 create the MPX G2-specific control signals.
MPX G2 has a five-channel footpedal A/D: the footpedal, three front-panel pots, and a 5V reference, used
to calibrate the front-panel pots. The A/D converter is the integrating type made from current source Q13,
comparator U10 and a 16-bit timer in the 2186.
To start the conversion, the 2186 brings RESET_PEDAL high, which turns on Q14, which discharges
capacitor C72 to less than 0.2V. Next, the 2186 selects whether to digitize the foot pedal or the pots. It
does this with a signal called SELECT_FOOT, which is bit 5 of register 1 inside the FPGA. When
SELECT_FOOT is high, the footpedal comparator output (FOOT_COMP) is routed to the 2186's interrupt
(PEDAL_ADC). When SELECT_FOOT is low, the pot comparator (POT_COMP) goes to PEDAL_ADC. If
a pot has been selected, the 2186 selects which pot with control lines SEL_ADCA and SEL_ADCB and
SEL_ADCC.
The 2186 then starts its timer and brings RESET_PEDAL low. C72 starts to charge from the current
source. Once the capacitor voltage exceeds the voltage to be digitized, PEDAL_ADC goes low. This
produces a high-level interrupt on the 2186, which disables the timer. At its convenience, the 2186 reads
the timer and derives the voltage on the pedal. This technique allows high resolution (14 bits) and low cost.
The input voltage range is 0-10 V. R101 puts the 5V-excitation voltage on the pedal ring, while preventing
excessive current draw from the 5V supply.
SHEET 6:
The MIDI in connector (J13) does double duty as the interface to the MIDI remote. In addition to the
standard MIDI input signals on pins 4 and 5, it sends a copy of MIDI out to pins 1 and 3, and also routes
power from the remote power jack (J14) to pins 6 and 7.
Opto_isolator U12 provides the necessary MIDI input isolation. U44 and Q16 create a copy of the MIDI
input signal, and send it to the MIDI thru jack (J12). Q15 and Q17 buffer the MIDI_OUT data from the
FPGA, and send it out J11 and J13. MIDI_OUT is pulled to ground with R105 because during initialization,
the FPGA IO pins are "weakly pulled up" as the Xilinx literature so accurately puts it.