5
LatticeEC Advanced Evaluation Board –
Lattice Semiconductor
Revision C User’s Guide
Table 5. V
CCIO
Selection Jumper
Depending on the optional devices installed, some sysIO banks may have restrictions.
Table 6. sysIO Bank Considerations
The following tables detail the various standards supported by the LatticeEC FPGA Input/Output (sysIO) struc-
tures. More information can be found in Lattice technical note number TN1056,
LatticeECP/EC sysIO Usage
Guide
, available on the Lattice web site at www.latticesemi.com.
Table 7. Mixed Voltage Support
For example, if V
CCIO
is connected to 3.3V, the input threshold for any pin within that sysIO bank may be configured
as 1.2V, 2.5V or 3.3V. Outputs are driven to the levels present on V
CCIO.
JP2
JP3
JP4
JP5
3.3V
1.2V
2.5V / 2.6V
Adjustable
VCCIO 0 (Bank0)
O O
O O
O O
O O
VCCIO 1
O O
O O
O O
O O
VCCIO 2
O O
O O
O O
O O
VCCIO 3
O O
O O
O O
O O
VCCIO 4
O O
O O
O O
O O
VCCIO 5
O O
O O
O O
O O
VCCIO 6
O O
O O
O O
O O
VCCIO 7 (Bank7)
O O
O O
O O
O O
Note: Shown with factory default settings.
Bank
Setting
0
2.5V only (FCRAM interface)
1
2.5V/2.6V if DDR SDRAM installed in socket J11
2
2.5V if SPI4.2 interface used
3
2.5V if SPI4.2 interface used, 3.3V if SPI3 configuration mode used
1
.
4
3.3V when PCI interface used
5
3.3V when PCI interface used
6
Any
7
Any
1. The LatticeEC Advanced Evaluation Board connects 2.5V to the V
CCIO
of Bank 3 to maxi-
mize functionality of the board with the SPI4.2 interface in the same bank as the sysCON-
FIG™ port. For optimum sysIO compatibility, 3.3V V
CCIO
is recommended for the
sysCONFIG port when interfacing to SPI3 Flash memory devices.
V
CCIO
Input sysIO Standards
Output sysIO Standards
1.2V
1.5V
1.8V
2.5V
3.3V
1.2V
1.5V
1.8V
2.5V
3.3V
1.2V
Yes
Yes
Yes
Yes
1.5V
Yes
Yes
Yes
Yes
Yes
1.8V
Yes
Yes
Yes
Yes
Yes
2.5V
Yes
Yes
Yes
Yes
3.3V
Yes
Yes
Yes
Yes