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LatticeEC Advanced Evaluation Board –
Lattice Semiconductor Revision C User’s Guide
SW3 is a momentary switch that, when pressed, forces the FPGA to start its programming cycle.
SW4, when in position 1 (up), connects the download cable to the SPI Flash so that the user can program the
Flash. When SW4 is in position 2 (down) the SPI Flash is connected to the LatticeEC FPGA; pressing and releas-
ing SW3 (assuming the configuration switch, SW5, is properly set) will configure the FPGA. The FPGA may be
accessed via the ispJTAG, using J6, no matter which position SW4 is in.
SW5 determines which type of device the FPGA expects to receive programming information from and whether the
FPGA will be master or slave during the transfer. Table 17 lists the possible configuration modes. A switch in the
down position produces a low (0), the up position produces a high (1).
Table 17. LatticeEC Configuration Settings
LEDs
Eight user-definable LEDs are provided on the upper left side of the board above SW1. These LEDs are each wired
to a separate general purpose I/O as defined in Table 18. The current limiting resistors associated with these LEDs
are wired to 2.5V but any I/O voltage up to 3.3V may be used. The LED will light when its associated I/O pin is
driven low.
Table 18. LEDs
SW5-1 SW5-2 SW5-3 Configuration Mode
0 0 0 SPI3 Flash
0 0 1 SPIX Flash
1 0 0 Master Serial
1 0 1 Slave Serial
1 1 0 Master Parallel
1 1 1 Slave Parallel
X X X ispJTAG (always available)
LED I/O Ball sysIO Bank
D1 B1 7
D2 C1 7
D3 D1 7
D4 E1 7
D5 F1 7
D6 G1 7
D7 H1 7
D8 J1 7