
13
LatticeEC Advanced Evaluation Board –
Lattice Semiconductor
Revision C User’s Guide
Proto Area
For general purpose I/Os, numerous test points are provided for direct access. The test points are labeled accord-
ing to the associated I/O pin location and are listed in Table 15.
Table 15. LatticeEC Pins Accessible at Test Points
Switches
Switch 1 (SW1) on the left side of the board is an eight-switch block that is part of the prototyping area. The pull-up
resistors associated with SW1 are wired to 2.5V, but any I/O voltage up to 3.3V may be used. A switch in the down
position produces a low (0), the up position produces a high (1). Table 16 shows the connections to the LatticeEC
I/O pins.
Table 16. SW1 Connections
SW2 is a momentary switch that the user can define for any purpose, such as a global reset. SW2 is wired to I/O
ball E23 (bank 4) and applies a low logic level when depressed.
A4 (0)
C8 (0)
F7 (0)
K3 (7)
N6 (6)
U1
1
(6)
AA11 (5)
AE11 (5)
A5 (0)
D1
2
(7)
F8 (0)
K4 (7)
P1
1
(6)
U2 (6)
AB4 (6)
AE12 (5)
A6 (0)
D2 (7)
F9 (0)
K5 (7)
P2 (6)
U3 (6)
AB6 (5)
AE2 (5)
A7 (0)
D4 (0)
G1
2
(7)
K6 (7)
P3 (6)
U4 (6)
AB7 (5)
AE3 (5)
A8 (0)
D6 (0)
G2 (7)
L1 (7)
P4 (6)
U5 (6)
AB8 (5)
AE5 (5)
A16 (1)
D7 (0)
G3 (7)
L2 (7)
P5 (6)
V1
1
(6)
AB9 (5)
AE6 (5)
A17 (1)
D8 (0)
G4 (7)
L3 (7)
P6 (6)
V2 (6)
AB10 (5)
AE7 (5)
B1
2
(7)
D9 (0)
G6 (7)
L4 (7)
R1
1
(6)
W2 (6)
AB11 (5)
AE8 (5)
B3 (0)
E1
2
(7)
G7 (0)
L5 (7)
R2 (6)
W21 (3)
AC4 (6)
AE9 (5)
B4 (0)
E2 (7)
G8 (0)
L6 (6)
R3 (6)
W22 (3)
AC5 (5)
AF2 (6)
B5 (0)
E3 (7)
G9 (0)
L7 (6)
R4 (6)
Y8 (5)
AC6 (5)
AF3 (5)
B6 (0)
E4 (7)
H1
2
(7)
M1 (7)
R5 (6)
Y9 (5)
AC7 (5)
AF5 (5)
B7 (0)
E6 (0)
H4 (7)
M2 (7)
R6 (6)
Y10 (5)
AC8 (5)
AF6 (5)
B8 (0)
E7 (0)
J1
2
(7)
M3 (7)
T1
1
(6)
Y11 (5)
AC9 (5)
AF7 (5)
C1
2
(7)
E8 (0)
J4 (7)
M4 (7)
T2 (6)
AA6 (5)
AC10 (5)
AF8 (5)
C4 (0)
E9 (0)
J5 (7)
M5 (6)
T3 (6)
AA7 (5)
AC11 (5)
AF9 (5)
C5 (0)
F1
2
(7)
J6 (7)
M6 (6)
T4 (6)
AA8 (5)
AC12 (5)
AF10 (5)
C6 (0)
F2 (7)
K1 (7)
N4 (6)
T5 (6)
AA9 (5)
AC23 (3)
AF11 (5)
C7 (0)
F3 (7)
K2 (7)
N5 (6)
T6 (6)
AA10 (5)
AE10 (5)
AF12 (5)
Note: sysIO Bank indicated in parenthesis.
1. Also connected to SW1. See Table 16 for details.
2. Also connected to LEDs. See Table 18 for details.
Switch
I/O Ball
sysIO Bank
SW1(1)
V1
6
SW1(2)
U1
6
SW1(3)
T1
6
SW1(4)
R1
6
SW1(5)
P1
6
SW1(6)
M1
7
SW1(7)
L1
7
SW1(8)
K1
7