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HDR-60 Base Board – Revision B
Introduction
The HDR-60 Base Board provides a low-cost evaluation and demonstration platform to evaluate, test and debug
image signal processing user designs or IP, including High Dynamic Range (HDR) cores targeted for the
LatticeECP3™-70 FPGA. The HDR-60 Base Board and NanoVesta Head Board have been designed to work
together as part of the HDR-60 Video Camera Development Kit. Connections are available on the HDR-60 Base
Board for the A-1000 HDRI sensor from Aptina, scalable to future sensors from Aptina, and adaptable to sensors
from other manufacturers by redesigning the add-on NanoVesta Head Board. The HDR-60 Base Board features a
LatticeECP3-70 FPGA in the 484-ball fpBGA package. The LatticeECP3 I/Os are connected to a rich variety of
both generic and application-specific interfaces described later in this document.
Important: This document (including the schematics in Appendix A) describes the HDR-60 Base Board marked as
Revision B. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice Semiconduc-
tor logo. The following are the changes from Revision A to Revision B.
• Added R136 and R137
• Installed R130 and R131
• Moved DVI_DDC_SCL signal to U2 pin D22
• Moved DVI_DDC_SDA signal to U2 pin G19
• Moved DVI_HPD signal to U2 pin C22
The LatticeECP3 is a third-generation device utilizing reconfigurable SRAM logic technology optimized to deliver
high-performance features such as an enhanced DSP architecture, high-speed SERDES and high-speed source
synchronous interfaces in an economical FPGA fabric. The LatticeECP3 devices also provide popular building
blocks such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked
Loops (DLLs), and advanced configuration support, including encryption, multi-boot capabilities and TransFR™
field upgrade features. The LatticeECP3 SERDES dedicated PCS functions, high jitter tolerance and low transmit
jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including
PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII), SATA I/II, OBSAI and CPRI. Transmit Pre-emphasis and
Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of
media.
For a full description of the LatticeECP3 FPGA, including data sheet, technical notes and more, see the Lattice
web site at
www.latticesemi.com/products/fpga/ecp3
.
Some common uses for the HDR-60 Base Board include:
• Security/surveillance and automotive camera applications
• Evaluation of the Helion NanoVesta Head Board and other camera sensors
• Applications using Aptina Head Boards
• Evaluation of Helion IONOS Imaging Pipeline IP cores
• Ethernet IP camera applications
• Evaluation of Teradek H.264 compression modules
Features
Key features of the HDR-60 Base Board include:
• SPI serial Flash device included for low-cost, non-volatile configuration storage
• DDR2 SDRAM: 16-bit data over a 32M address space
• Tri-speed (10/100/1000 Mbit) Ethernet PHY with RJ-45 (includes 12 core magnetics)
