9
HDR-60 Base Board – Revision B
Parallel Connector (J2)
The LatticeECP3 (U2) bank 1 receives parallel video signals from connector J2. The signal connections between
the LatticeECP3 device and the HiSPi connector are shown in Table 7.
Table 7. LatticeECP3 (U2) Interface to Parallel Connector J2
J2 Pin
LatticeECP3
I/O BGA Ball
sysIO Bank
Parallel Signal
Differential Signal
16
J20
2
DOUT0
SLVS_8N
20
G22
2
DOUT1
SLVS_9N
15
F22
2
DOUT2
SLVS_11N
19
J18
2
DOUT3
SLVS_10N
14
A16
1
DOUT4
—
18
J19
2
DOUT5
SLVS_8P
13
C16
1
DOUT6
—
17
E22
2
DOUT7
SLVS_11P
22
G21
2
DOUT8
SLVS_9P
24
G14
1
DOUT9
—
21
J17
2
DOUT10
SLVS_10P
23
C17
1
DOUT11
—
10
C12
1
PIXCLK
—
9
A19
1
EXTCLK_FPGA
—
11
A18
1
LINE_VALID
—
12
B16
1
FRAME_VALID
—
25
B18
1
TRIGGER
—
27
A17
1
RESET_BAR
—
29
F16
1
OUTPUT_EN_BAR
—
31
F15
1
STANDBY
—
26
G15
1
SADDR
—
28
D15
1
SCLK
—
30
C15
1
SDATA
—
32
E15
1
OSC_ENABLE
—
4
A12
1
VDDIO_rP
—
Aptina Head Board Connector
Connectors J7 and J8 make up the Aptina Head Board connector. They are described below. Note that jumpers J5
and J6 may be required to be in the 2 and 3 positions if using Aptina DevWare software. Contact Aptina for details
on running DevWare on the HDR-60 Base Board.
Dual Row Connector (J7)
The LatticeECP3 (U2) bank 0 interfaces to the Aptina dual row connector (J7) as shown in Table 8.
Table 8. LatticeECP3 (U2) Interface to Aptina Dual Row Connector (J7)
J7 Pin
LatticeECP3 I/O BGA Ball
sysIO Bank
Signal
1
C8
0
HEAD_DOUT0
2
C7
0
HEAD_DOUT1
3
F9
0
HEAD_DOUT2
4
E9
0
HEAD_DOUT3
5
C9
0
HEAD_DOUT4
