6
HDR-60 Base Board – Revision B
reference. By doing this, the regulator output voltage remains at a constant voltage value independent of the load
driven. Each regulator output voltage follows this equation:
V
out
= (1 + resistor ratio) x (regulator internal reference voltage)
See the LT3503 and LT3508 device data sheets for additional details about these devices.
The 2.5 V regulator output voltage can also be set to 1.8 V or 3.3 V by adding a shorting jumper on J4, as shown in
Table 2. With no jumper on J4, the voltage divider is set by R53 and R5 and this divider sets up a nominal 2.5 V
output voltage. When a shorting jumper is added to J4, the R56 and R51 resistors will be placed in parallel with
either R53 or R5, which then changes the resistor divider ratio, and this changes side 1 of the U10 regulator output
voltage to become 1.8 V or 3.3 V depending on the placement of the shorting jumper on J4.
The SERDES 1.2 V regulators (U4) are low dropout linear types that deliver a constant 1.2 V output voltage when
powered by the 3.3 V input voltage. In contrast to the switching regulators discussed above, the U4 linear regulars
do not generate switching noise, so they are a good choice for powering the LatticeECP3 SERDES to give the low-
est jitter generation. Also, U4 does not use resistor divider networks to set the output voltage, instead U4 is set up
to directly copy its own internal 1.215 V reference voltage to its outputs. The U4 regulator outputs are available for
testing at test points PP5 and PP6. See the LT3029 device data sheets for additional details about this device.
When using the various I/O test points located around the board, be sure to not exceed the
LatticeECP3 Family
Data Sheet
specified absolute maximum rating for Output Supply Voltage VCCIO range of -0.5 V to +3.75 V, or
damage to the device may occur. Also, for I/O input capability of the various I/O standards supported by the
LatticeECP3 sysIO structures, see the
LatticeECP3 sysIO Usage Guide
.
LatticeECP3 I/O Bank Voltages
Most of the bank voltages on the LatticeECP3 (U2) have been hard-wired to specific power supply values. Excep-
tions to this are banks 1 and 2 which can be set to other values used to power the sensor boards that plug into the
parallel connector (J2) and HiSPi connector (J1). This is shown in Table 3.
Table 3. LatticeECP3 (U2) Bank Voltage Settings
LatticeECP3 Bank VCCIO
Voltage
Comment
0
3.3 V
Aptina Head Board
1 and 2
Adjustable
Sensor attached to J1 and J2
1.8 V: Jumper on J4 pins 1-2
2.5 V: No jumper on J4 (default)
3.3 V: Jumper on J4 pins 2-3
3
1.8 V
DDR2
Quad A
1.2 V
SERDES
6
3.3 V
Teradek MPEG Encoder
7
3.3 V
Ethernet
8
3.3 V
LatticeECP3 programming
