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4

 HDR-60 Base Board – Revision B

Initial Setup and Handling

The following is recommended reading prior to removing the evaluation board from the static shielding bag and 
may or may not apply to your particular use of the board.

CAUTION: The devices on the board can be damaged by improper handling.

The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures 
within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example 
of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their 
designed in protection. For example: higher static voltages, as well as lower voltages with lower series resistance 
or larger capacitance than the respective ESD specifications can potentially damage or degrade the devices on the 
evaluation board.

As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while han-
dling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a 
while, it is best to put it back in the static shielding bag. Please save the static shielding bag and packing box for 
future storage of the board when it is not in use. 

When reaching for the board, it is recommended that you first touch the ground plane of the board (for example, the 
metal shielding of the HDMI connector). This will neutralize any static voltage difference between your body and the 
board prior to any contact with signal I/O.

CAUTION: To minimize the possibility of ESD damage, the first and last electrical connections to the board should 
always be from test equipment chassis ground to the ground plane of the board.

Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment 
to the ground plane of the board. Connecting the board ground to test equipment chassis ground will decrease the 
risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when 
unplugging cables from the evaluation board, the last connection unplugged, should be the chassis GND connec-
tion to the evaluation board GND. If you have a signal source that is floating with respect to chassis GND, attempt 
to neutralize any static charge on that signal source prior to attaching it to the evaluation board.

If you are holding or carrying the board when it is not in a static shielding bag, please keep one finger on the ground 
plane of the board, for example the metal shielding of the HDMI connector. This will keep the board at the same 
voltage potential as your body until you can pick up the static shielding bag and put the board back in it.

Electrical, Mechanical, and Environmental Specifications

The nominal board dimensions are 203.2 mm x 42 mm (8.000” x 1.654”). Additional mechanical board dimension 
information is included on the mechanical drawing shown in Appendix A, Figure 24. On the physical board itself, 
connectors include pin 1 indictors as either an arrow, or triangle point near pin 1 on the outer layer silk screen. The 
environmental specifications are as follows:

• Operating temperature: 0 °C to 55 °C

• Storage temperature: -40 °C to 75 °C

• Humidity: <95% without condensation

• 11 V to 18 V DC (20 watts max.) 

Содержание HDR-60

Страница 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Страница 2: ...April 2014 Revision EB70_01 2 HDR 60 Base Board Revision B User s Guide...

Страница 3: ...performance features such as an enhanced DSP architecture high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric The LatticeECP3 devices also provide popular build...

Страница 4: ...nnectors attached to the LatticeECP3 provide a means to investigate applications developed for High Dynamic Range image signal pro cessing The board also provides several different interconnections an...

Страница 5: ...CAUTION To minimize the possibility of ESD damage the first and last electrical connections to the board should always be from test equipment chassis ground to the ground plane of the board Before co...

Страница 6: ...rs then pro vide the necessary supply voltages 3 3 V 2 5 V 1 8 V 1 2 V For proper operation the 12 V DC power applied at J10 should be within the range of 11 V min to 18 V max The requirements for the...

Страница 7: ...the low est jitter generation Also U4 does not use resistor divider networks to set the output voltage instead U4 is set up to directly copy its own internal 1 215 V reference voltage to its outputs...

Страница 8: ...ch as J1 J2 J7 J8 and J9 which could also be considered as available prototype connectors when they are not in use Crystal Oscillators There are two crystal oscillators and two MEMS based oscillators...

Страница 9: ...t type to LVDS with differential 100 ohm termination The signal connections between the LatticeECP3 device and the HiSPi connector are shown in Table 6 Table 6 LatticeECP3 U2 Interface to HiSPi Connec...

Страница 10: ...9 A19 1 EXTCLK_FPGA 11 A18 1 LINE_VALID 12 B16 1 FRAME_VALID 25 B18 1 TRIGGER 27 A17 1 RESET_BAR 29 F16 1 OUTPUT_EN_BAR 31 F15 1 STANDBY 26 G15 1 SADDR 28 D15 1 SCLK 30 C15 1 SDATA 32 E15 1 OSC_ENABLE...

Страница 11: ...bank 6 I Os connect to the Teradek MPEG Encoder Connector J9 The signal connections are shown in Table 10 6 C10 0 HEAD_DOUT5 7 B7 0 HEAD_DOUT6 8 A7 0 HEAD_DOUT7 9 B8 0 HEAD_DOUT8 10 A8 0 HEAD_DOUT9 13...

Страница 12: ...J12 upper USB port The J12 upper USB port connects to a FTD2232D USB transceiver U5 that can produce JTAG signals able to drive the LatticeECP3 device U2 Given this the ispVM System software can detec...

Страница 13: ...powered by an on board 1 8 V regulator with a 0 9 V midpoint bias termination regulator U12 The evaluation board includes terminations for address command and data signals The suggested configuration...

Страница 14: ...use the PHY to evaluate a custom MAC solution During power up the resistors R21 R22 R23 R24 R25 R103 R105 and R107 set the initialized PHY configura tion to auto negotiate full duplex 10 100 1000Base...

Страница 15: ...ndix A and the Broadcom BCM54810 Data Sheet for detailed information about the operation of the Ethernet PHY interface on this device Refer to Table 15 for a description of the Ethernet PHY GMII conne...

Страница 16: ...t J3 as described in Appendix C Given that you might want to download to either the LatticeECP3 SRAM or the SPI Flash separate LatticeECP3 download procedures will follow that cover each type of downl...

Страница 17: ...t LFE3 70EA See Figure 5 Figure 5 ispVM New Scan Configuration Setup 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the pack...

Страница 18: ...Bitstream Download Operation Successful LatticeECP3 SRAM Configuration Using SPI Flash and USB Cable at J12 The LatticeECP3 SRAM can be configured easily using the ispVM System software to program the...

Страница 19: ...ns select LFE3 70EA 7 Click Edit Edit Device to edit the device A Device Information window will be opened Click the Select but ton and select the package type 484 ball fpBGA then click OK 8 Click the...

Страница 20: ...the bitstream download progress indictor will pop up as shown in Figure 13 When using the built in USB down load cable it will take about two minutes to erase program and verify the bitstream loaded p...

Страница 21: ...CP3 U2 from the external SPI Flash U9 in two seconds and the DONE LED LED3 will light up References HDR 60 Video Camera Development Kit web page DS1021 LatticeECP3 Family Data Sheet HB1009 LatticeECP3...

Страница 22: ...3 70EAHDR60 EVN 21 HDR 60 Base Board Revision B Ordering Information Technical Support Assistance e mail techsupport latticesemi com Internet www latticesemi com Revision History Date Version Change S...

Страница 23: ...Bit Sheet 9 Teradek MPEG Encoder USB Sheet 8 Nanovesta Head Board Sheet 4 Nanovesta Head Board Title Size Project Rev Date Sheet of Lattice Semiconductor Corporation 5555 N E Moore Court Hillsboro Or...

Страница 24: ...sboro Oregon 97124 HDR 60 Base Board Schematic B Voltage Regulators B 2 10 Wednesday September 21 2011 R51 22_1K 0603SMT R50 51k C68 PP7 1 2 C8 22uF 6 3V R44 51k C81 C85 22uF 6 3V PP4 1 2 C74 C207 22p...

Страница 25: ...56 T12 57 P2 58 E21 59 C11 60 AA12 61 Y16 62 V14 63 AA16 64 H18 65 M12 66 R5 67 W16 68 AB22 69 H8 70 N10 71 E14 72 U10 73 F2 98 N11 97 K13 96 B9 95 G12 94 V2 93 K8 92 M16 91 Y4 90 N12 89 AA7 88 U13 8...

Страница 26: ...F7 NC58 F8 NC59 F9 TDO F10 NC62 G2 REGSUPPLY G3 NC64 G4 NC65 G5 TEST2 G8 TEST3 G9 RDAC H1 NC72 H2 NC73 H3 NC77 H7 TEST0 H8 TEST1 H9 TRD 0 K1 TRD 0 K2 TRD 1 K3 TRD 1 K4 TRD 2 K5 TRD 2 K6 TRD 3 K7 TRD 3...

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