12
HDR-60 Base Board – Revision B
See the
“Configuring/Programming the Board”
section of this document for details on how to download bitstreams
into the LatticeECP3 device. See
www.latticesemi.com/hdr60
for additional downloadable project files and bit-
streams designed for use with this board.
LEDs
There are three LEDs on the HDR-60 Base Board that are used to show the programming state of the
LatticeECP3. See Table 11 for information on the programming state LEDs.
Table 11. Programming LEDs
LED
Pin
Color
Function
LED1
PROGRAMN
Red
On when signal is low
LED2
INITN
Red
On when initializing
LED3
DONE
Green
On when configuration is complete
DDR2 Memory
The HDR-60 Base Board is equipped with an 84-ball BGA DDR2 SDRAM such as the IS43DR16320B, which pro-
vides memory resources with16 bits of data width that span a 32M address space. The DDR2 memory is powered
by an on-board 1.8 V regulator with a 0.9 V midpoint bias termination regulator (U12). The evaluation board
includes terminations for address, command and data signals. The suggested configuration is to set the DDR2
SDRAM (U1) for internal 150 ohms ODT, and the LatticeECP3 (U2) address, control and data signals to slow slew,
8 ma, with no ODT. This gives a low-noise, low-power DDR2 memory configuration usable to over 400 MT/s.
Table 12 shows the pin connections for both the LatticeECP3 (U2) and DDR2 SDRAM (U1).
Table 12. LatticeECP3 Interface to DDR2 SDRAM
Signal Name
LatticeECP3 I/O Pin (U2)
sysIO Bank
DDR2 SDRAM Pin (U1)
DDR2_DQ0
R22
3
G8
DDR2_DQ1
R20
3
G2
DDR2_DQ2
T20
3
H7
DDR2_DQ3
T22
3
H3
DDR2_DQ4
R21
3
H1
DDR2_DQ5
N19
3
H9
DDR2_DQ6
P22
3
F1
DDR2_DQ7
M19
3
F9
DDR2_DM0
N20
3
F3
DDR2_DQS0_P
N18
3
F7
DDR2_DQS0_N
P19
3
E8
DDR2_DQ8
Y21
3
C8
DDR2_DQ9
V22
3
C2
DDR2_DQ10
W22
3
D7
DDR2_DQ11
W21
3
D3
DDR2_DQ12
U22
3
D1
DDR2_DQ13
Y22
3
D9
DDR2_DQ14
R16
3
B1
DDR2_DQ15
P17
3
B9
DDR2_DM1
R18
3
B3
DDR2_DQS1_P
T21
3
B7
DDR2_DQS1_N
U20
3
A8
DDR2_VREF
P20
3
J2
