Kontron EPIC/CE, Руководство пользователя

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7 ISA and PCI Bus Expansion
Kontron User's Guide EPIC/CE 25
7 ISA and PCI Bus Expansion
The design of the EPIC/CE follows the standard EPIC (
E
mbedded
P
latform for
I
ndustrial
C
omputing) form
factor and offers ISA- and PCI-bus signals. The PC/104-Plus standard is downward compatible with
PC/104 and enables the use of standard PC/104 and PC/104-Plus adapter cards as on-top modules.
7.1 PC/104 Bus (ISA part)
The PC/104 bus consists of two connectors that use 104 pins in total.
®
XT bus connector (64 pins)
®
AT bus connector (40 pins, which is optional for 16-bit, data-bus system)
The pin-out of the PC/104 bus connectors corresponds to the pin-out of the ISA bus connectors with
some added ground pins. The two PC systems with different form factors are electrically compatible.
The
XT bus connector
, Row A and B.
The corresponding 64-pin female header (ISA bus = 62pins) has two added ground pins at the end of the
connector (Pin A32 and Pin B32). The pin-out between PC/104 bus and XT ISA bus is identical between
A1 - A31 and B1 - B31.
The
AT bus extension connector
, Row C and D.
The corresponding 40-pin female header (ISA bus = 36 pins) has four added ground pins, including two
on each side of the connector. To avoid confusion, the first two pins are defined as Pin C0 and Pin D0.
The additional ground pins at the end of the connector are defined as C19 and D19. The pin-out between
PC/104 bus and AT ISA bus is identical between C1 - C18 and D1 - D18.
7.1.1 PC/104 Connectors
The EPIC/CE features the XT bus and AT bus extension on two, dual-row socket connectors with a 2.54mm
x 2.54mm grid (0.1" x 0.1").
The PC-104 bus is available through Connectors J16B and J16C.
A description of the signals, including electrical characteristics and timings is beyond the scope of this
document. Please refer to the official ISA bus and PC/104 specifications for more details.
7.1.2 PC/104 Configuration
When using add-on boards on the PC/104 bus, make sure that there are no resource conflicts in the
system. Carefully choose hardware interrupts, DMA channels, and memory and I/O address ranges to
avoid resource conflicts, which are often the reason for a board or a feature not functioning correctly.
See Appendix A: System Resource Allocation for information about the resources already used by the
EPIC/CE.