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CP6940 User Guide
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3.4.5.5
J5 Connector
•
PICMG 2.16 Link Port 9 to Link Port 19 (10/100/1000Base-T)
3.5
Write Protection Feature
TThe CP6940 supports hardware driven write protection for all non-volatile memory devices. The protection is imple-
mented by disabling the write enable signal, for all non-volatile memory devices.
Table 12:
Connector J5 Pinout
Pin
Row A
Row B
Row C
Row D
Row E
Row F
22
FL_DA19-
GND
FL_DC19-
GND
21
FL_DB19-
GND
FL_DD19-
GND
20
FL_DA18-
GND
FL_DC18-
GND
19
FL_DB18-
GND
FL_DD18-
GND
18
FL_DA17-
GND
FL_DC17-
GND
17
FL_DB17-
GND
FL_DD17-
GND
16
FL_DA16-
GND
FL_DC16-
GND
15
FL_DB16-
GND
FL_DD16-
GND
14
FL_DA15-
GND
FL_DC15-
GND
13
FL_DB15-
GND
FL_DD15-
GND
12
FL_DA14-
GND
FL_DC14-
GND
11
FL_DB14-
GND
FL_DD14-
GND
10
FL_DA13-
GND
FL_DC13-
GND
9
FL_DB13-
GND
FL_DD13-
GND
8
FL_DA12-
GND
FL_DC12-
GND
7
FL_DB12-
GND
FL_DD12-
GND
6
FL_DA11-
GND
FL_DC11-
GND
5
FL_DB11-
GND
FL_DD11-
GND
4
FL_DA10-
GND
FL_DC10-
GND
3
FL_DB10-
GND
FL_DD10-
GND
2
FL_DA9-
GND
FL_DC9-
GND
1
FL_DB9-
GND
FL_DD9-
GND