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CP6940 User Guide
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Power Considerations
The power considerations presented in this chapter must be taken into account by system integrators when specifying
the CP6940 system environment.
The CP6940 has been designed for optimal power input and distribution. Still it is necessary to observe certain criteria
essential for application stability and reliability. The board is supplied by 3.3V and 5.0V from the backplane. All supply
voltages from the backplane are enabled with a predefined ramp-up time. The inrush current is limited by Hot-Swap
controllers.
The table below indicates the absolute maximum input voltage ratings that must not be exceeded. Power supplies to be
used with the CP6940 should be carefully tested to ensure compliance with these ratings.
Power consumption: below 55 W.
5.0 V VIN +5%/-3%, designed for maximum load 5.50A (27.50W)
3.3 V VIN +5%/-3%, designed for maximum load 10.00A (33W)
6.1
Backplanes
Backplanes to be used with the CP6940 must be adequately specified. The backplane must provide optimal power distri-
bution for the +3.3 V and +5 V power inputs. Input power connections to the backplane itself should be carefully specified
to ensure a minimum of power loss and to guarantee operational stability. Long input lines, under-dimensioned cabling
or bridges, high resistance connections, etc. must be avoided. It is recommended to use POSITRONIC or M-type connector
backplanes and power supplies where possible.
Backplanes does not need any 12V supply.
Table 34: Maximum Input Power Voltage Limits
Voltage Rail
Operation Mode
Maximum Current
V_3V3_CPCI
24x 1Gbps traffic rear
2x QSFP+ for 40G, 4x 10G SFP+, 2x 1G SFP ports
8.00A
V_5V0_CPCI
24x 1Gbps traffic rear
2x QSFP+ for 40G, 4x 10G SFP+, 2x 1G SFPports
4.50A
