886LCD-M Family
KTD-00474-E
Public User Manual
Date: 2005-05-24
Page
29 of 78
4.4.3 AGP/DVO
connector
Note
Type
Signal
PIN
Signal
Type
Note
OVRCNT B1
A1
+12V
PWR
PWR
+5V B2
A2
TYPEDET
PWR
+5V B3
A3 RSVD
USB+ B4
A4
USB-
PWR
GND B5
A5 GND
PWR
INTB B6
A6 INTA
AGPCLK B7
A7
RST-
GREQ B8
A8 GGNT
PWR
+3.3V B9
A9 +3.3V
PWR
ST0 B10
A10 ST1
ST2 B11
A11 RSVD
I
RBF B12
A12 PIPE
I
PWR
GND B13
A13 GND
PWR
RSVD B14
A14
WBF
I
I
ADD_ID0 B15
A15 ADD_ID1
I
PWR
+3.3V B16
A16 +3.3V
PWR
I
ADD_ID2 B17
A17 ADD_ID3
I
I
ADD_RS B18
A18 ADD_RS
PWR
GND B19
A19 GND
PWR
I
ADD_ID4 B20
A20 ADD_ID5
I
I
ADD_ID6 B21
A21 ADD_ID7
I
RSVD B22
A22 RSVD
PWR
GND B23
A23 GND
PWR
PWR
3V3AUX B24
A24
RSVD
PWR
+3.3V B25
A25 +3.3V
PWR
DVOC_Fld/Stl B26
A26
DVOBC_Intr-
DVOC_D10 B27
A27 DVOC_D11
PWR
+3.3V B28
A28 +3.3V
PWR
DVOC_D8 B29
A29 DVOC_D9
DVOC_D6 B30
A30 DVOC_D7
PWR
GND B31
A31 GND
PWR
D B32
A32
DVOC_Clk-
DVOC_D4 B33
A33 DVOC_D5
PWR
+1.5V B34
A34 +1.5V
PWR
DVOC_D2 B35
A35 DVOC_D3
DVOC_D0 B36
A36 DVOC_D1
PWR
GND B37
A37 GND
PWR
DVOC_Hsync B38
A38 DVOC_Blank-
ADD_RS B39
A39 DVOC_Vsync
PWR
+1.5V B40
A40 +1.5V
PWR
M_I2CClk B41
A41 M_DVI_Data
M_I2CData B46
A46 M_DVI_Clk
PWR
+1.5V B47
A47
M_DDCData
GPERR B48
A48
PME
PWR
GND B49
A49 GND
PWR
GSERR B50
A50 ADD_Detect
DVOB_Blank- B51
A51
M_DDCClk
PWR
+1.5V B52
A52 +1.5V
PWR
DVOB_Fld/Stl B53
A53 DVOBC_ClkInt
DVOB_D10 B54
A54 DVOB_D11
PWR
GND B55
A55 GND
PWR
DVOB_D8 B56
A56 DVOB_D9
DVOB_D6 B57
A57 DVOB_D7
PWR
+1.5V B58
A58 +1.5V
PWR
D B59
A59
DVOB_Clk-
DVOB_D4 B60
A60 DVOB_D5
PWR
GND B61
A61 GND
PWR
DVOB_D2 B62
A62 DVOB_D3
DVOB_D0 B63
A63 DVOB_D1
PWR
+1.5V B64
A64 +1.5V
PWR
DVOB-Vsync B65
A65 DVOB_Hsync
VREFCG B66
A66 VREFGC
The AGP buffers operate only in 1.5V mode (not 3.3-V tolerant). The AGP interface supports 1x/2x/4x AGP
signaling and 2x/4x Fast Writes.