IRQ Status Registers 1 and 2
6-13
IRQ Status Registers 1 and 2
The IRQ Status registers are read-only. The I/O addresses of the IRQ
Status register bits for the C0 and C3 channels of each group are the same
as those shown for the IRQ Control register.
A 1 for a particular IRQ Status register bit indicates the issue of an IRQ
signal by the corresponding input channel. This bit remains a 1 until
cleared and disabled.
The following two lines of BASIC code are an example of commands to
read the settings of all IRQ Status register bits in a PIO-SSR-120 whose
base I/O address is 300h.
ST1 = INP (&H314)
’Read IRQ status of J1 to J4
’groups
ST2 = INP (&H315)
’Read IRQ status of J5 group
Table 6-7. Addresses of IRQ Control Register Bits for a
PIO-SSR-120
Input Channel
Bit #
I/O Address
J1-C0
0
Base a14h
J1-C3
1
Base a14h
J2-C0
2
Base a14h
J2-C3
3
Base a14h
J3-C0
4
Base a14h
J3-C3
5
Base a14h
J4-C0
6
Base a14h
J4-C3
7
Base a14h
J5-C0
0
Base a15h
J5-C3
1
Base a15h
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