2-3
A0 to A7
B0 to B7
C4 to C7
C0 to C3
J1
I/O Mode
Selector
A0 to A7
B0 to B7
C4 to C7
C0 to C3
J2
I/O Mode
Selector
A0 to A7
B0 to B7
C4 to C7
C0 to C3
J3
I/O Mode
Selector
A0 to A7
B0 to B7
C4 to C7
C0 to C3
J4
I/O Mode
Selector
J5 Data Buffer
Port A
Port B
Port C
A0 to A7
B0 to B7
C4 to C7
C0 to C3
J5
I/O Mode
Selector
Address
Decoder
Data
Bus
Buffer
Data Bus
Control Bus
IRQ
Control
Circuit
IRQ
Levels
3 to 7
9 to 12
14, 15
D7 to D0
SA15
to
SA5
Figure 2-3. Block Diagram of PIO-SSR-120
C0 and C3
C0 and C3
C0 and C3
C0 and C3
C0 and C3
J4 Data Buffer
Port A
Port B
Port C
J3 Data Buffer
Port A
Port B
Port C
J2 Data Buffer
Port A
Port B
Port C
J1 Data Buffer
Port A
Port B
Port C
I/O
Control
Circuit
Control
Bus
Buffer
SA4
to
SA0
RESET
IOW
IOR
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