Maintenance
7-10
Table 7-4
Relay control checks
Step
Item/component
Signal
Comments
1
2
3
4
5
6
7
U103 pin 23
U137 pin 5
U137 pin 3
U137 pin 6
U130 pin 1
U137 pin 7
U137 pin 18
SELECT VIA
CLRADDR
NEXTADDR
IDDATA
SELECT RELAYDATA
CLK
RELAYDATA
Low going pulses (1kHz).
High logic pulse at start of each matrix card ID byte transfer
sequence on power-up.
Low logic pulse before each byte transfer from matrix card on
power-up.
Matrix card ID logic pulse train on power-up.
Low going pulse when program #1 is running.
Eight low-going pulses (1.79MHz square wave) after each
SELECT RELAYDATA pulse.
Logic pulses to load relay drivers on matrix card.
Note: See Figure 7-5 for waveforms of steps 5 through 7.
Table 7-5
Display interface checks
Step
Item/component
Signal
Comments
1
2
3
4
5
6
U103 pin 23
U103 pin 18
U125 pin 6
U125 pin 3
U126 pin 6
U126 pin 2
SELECT VIA
FPCLK
DISPCLK
KEYCLK
DISPDATA
KEYDATA
Low going pulses (1kHz).
Base frequency of 895kHz with ten sets of pulses every 1ms.
Base frequency of 895kHz with nine sets of pulses every 1ms.
Base frequency of 895kHz with one set of pulses every 1ms.
See Figure 7-6.
See Figure 7-6.
Table 7-6
Digital I/O checks
Step Item/component
Signal
Comments
The following mother board signals are referenced to digital common.
1
2
3
4
5
6
U108 pin 23
U108 pins 10-17
U133 pin 1
U133 pins 3, 4, 7, 8, 13, 14, 17, 18
U1119 pin 11
U119 pins 2, 5, 6, 9, 12, 15, 16, 19
SELECT_PIA
SW(0-7)
SELECT_LO_INPUT
LO_IN(0-7)
SELECT_LO_OUT
LO_OUT(0-7)
Low going pulses (1kHz).
Logic low when programmed low.
Low going pulses (5kHz) when digital input is dis-
played.
Logic high when port disconnected.
Pair of low going pulse trains when digital output is
displayed.
Low logic pulse selects card for data transfer
sequence.
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