Principles of Operation
6-11
6.5.1 Display data
The mother board sends display data (DISPDATA) to the
front panel control board serially. Two bytes are required to
select the column and row.
The cathodes are driven by U205 and U206. The anodes are
driven by source drivers U203-U204 (UCN5895A) con-
nected in a serial data chain. While new data is being sent to
the display drivers, the BLANKOUT line is set high to dis-
able the outputs. Display data is first shifted into the serial-
to- parallel converter U208 (74HCT164) and then to the
source drivers.
Four parallel outputs of U208 are decoded by the 4-to-16
decoder U207 (74HCT154). The outputs of this decoder
drive the display cathodes through sink drivers U205-U206
(2597A).
6.5.2 Front panel keys
The front panel keys are SPST normally-open pushbutton
switches. Each key is connected to one of the column drive
outputs of decoder U207 (74HCT154) through a diode. The
diodes isolate the columns from each other in case more than
one key is pressed. As the display is multiplexed, each key
column is pulled low in its turn, and the other columns float.
Each key is connected to Vcc through a pull-up resistor and
to one of the inputs of parallel-to-serial converter U209
(74HCT165). The load input of U209 is connected to the
BLANKOUT signal, so each time new data is sent to the dis-
play, another key gets latched into U209.
6.5.3 Display interface
The display interface circuitry of the mother board generates
clock signals and communicates serial data for the front pan-
el display and keyboard. The shift register of U103 (6522A
VIA) controls the display and reads the key array. Pin CB1 is
the clock signal (FPCLK), and pin CB2 is the data signal
(FPDATA).
Signal FPCLK is generated for both serial output (display)
and serial input (keyboard) operations. This single bi-direc-
tional port is converted to two uni-directional ports by two
OR gates of U125 (74HCT32), two tri-state drivers of U126
(74HCT125), and a NAND gate of U127 (74HCT00) used as
an inverter.
When the low true KEY signal (generated on VIA pin PB1)
is asserted, DISPCLK is held high, KEYCLK follows
FPCLK, the KEYDATA driver (U126) is enabled, and the
DISPDATA driver (U126) is disabled.
When the low true KEY signal is negated, the KEYCLK sig-
nal is held high, and the DISPCLK signal follows FPCLK.
The KEYDATA driver is also disabled, and the DISPDATA
driver is enabled. The remaining signal that goes to the dis-
play board, BLANK, is generated by VIA output pin PB0.
6.5.4 Refresh display/read keyboard
The refresh display/read keyboard sequence is as follows:
NOTE
During power-on hardware initialization,
the U103 shift register (6522A VIA) is
configured for output, and the low true
KEY signal is negated.
1. Set the BLANK line high.
2. Send two bytes of DISPDATA out the VIA shift register
to drive the next column in the multiplex sequence.
3. Set the BLANK line low.
4. Configure the VIA shift register for input.
5. Assert the low true KEY line.
6. Read the VIA shift register to cause the KEYDATA to be
shifted into the VIA.
7. Read the VIA shift register again to get the byte of
KEYDATA.
8. Negate the low true KEY line.
9. Configure the VIA shift register for output.
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