Principles of Operation
6-3
6.3.1 Reset circuit
The reset circuit, which is based on an 8211 (or 6728) volt-
age detector (U111), senses the output of the power supply.
When the output drops below approximately 4.6V, the 8211
asserts the RESET (low true) line. Two 1% resistors (R115
and R116) form a voltage divider, which is calibrated to
match the comparator threshold voltage of the 8211 by either
removing or leaving in R117, which is in parallel with R116.
During power-off or brownout conditions, the RESET line
must be asserted before the power supply drops into the com-
parator threshold range (4.25 to 4.5 volts) of the DS-1210
non-volatile RAM controller (U114). During power-up,
capacitor C115 is charged up to delay the RESET line going
high for 110 to 260ms.
6.3.2 Address decoding
U117, a 16P8A programmable array logic (PAL) chip,
decodes microprocessor address lines A15-A12 for the 32K
EPROM ($8000-$FFFF) and the 32K bytes of bank-selected
RAM ($0000-$2FFF). Bank selection is used so that the
RAM appears as 12K bytes of address space to the
microprocessor.
U117 also decodes the three bank-select lines (BS3-BS0)
from the PB6-PB4 outputs of U103, a 6522A versatile inter-
face adapter (VIA). The RAM is decoded as 8K bytes
($0000-$1FFF) and six 4K byte banks, which appear to the
microprocessor at addresses $2000-$2FFE. This lets the
microprocessor select one of the six 4K byte banks.
Address decoding for peripheral devices on the microproces-
sor bus is performed by another 16P8A PAL (U116). Periph-
eral devices are decoded at 16-byte intervals in the address
range of $3800-$38FF. These include, for example, a 6522A
VIA, a 65C21 peripheral interface adapter (PIA), and a
68B50 asynchronous communication interface adapter
(ACIA).
6.3.3 Memory
The 32K bytes of instrument operation software are stored in
U105 ($8000-$FFFF), which is a 27256 EPROM.
U106 ($0000-$2FFF) is a 32K byte static CMOS RAM chip
used for storing relay setups and as a scratchpad during nor-
mal operation. Its power source and chip enable lines are
routed through U114, a DS-1210 NVRAM controller. Figure
6-3 shows a simplified schematic of the RAM and battery
backup circuitry.
The NVRAM controller performs the functions of switching
the RAM power source between Vcc and the lithium battery
(BT101). It also disables chip enable (CE) to the RAM when
Vcc is outside the specified limits (paragraph 6.3.1).
In addition, if the battery power goes below a specified limit
while Vcc is not present, a DS-1210 chip normally inhibits
the second chip enable signal to the RAM after Vcc is
restored. Since this feature is not used in the Model 708A,
the software always does a dummy read of memory locations
$0000-$0001 on power-up to get past the second chip enable
cycle. This permits the Model 708A to operate properly with
no battery, or if the battery has been replaced.
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